JPWO2021042110A5 - - Google Patents

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JPWO2021042110A5
JPWO2021042110A5 JP2022510899A JP2022510899A JPWO2021042110A5 JP WO2021042110 A5 JPWO2021042110 A5 JP WO2021042110A5 JP 2022510899 A JP2022510899 A JP 2022510899A JP 2022510899 A JP2022510899 A JP 2022510899A JP WO2021042110 A5 JPWO2021042110 A5 JP WO2021042110A5
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circuit
clock
physical layer
data
receive
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JP2022544985A (ja
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Priority claimed from CN201910785140.7A external-priority patent/CN112422219A/zh
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JP2022510899A 2019-08-23 2020-08-05 イーサネットインターフェース、並びに関連するシステム、方法、及びデバイス Pending JP2022544985A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
CN201910785140.7A CN112422219A (zh) 2019-08-23 2019-08-23 以太网接口和相关系统、方法和设备
CN201910785140.7 2019-08-23
US16/684,428 US11671521B2 (en) 2019-08-23 2019-11-14 Ethernet interface and related systems, methods and devices
US16/684,428 2019-11-14
PCT/US2020/070367 WO2021042110A1 (en) 2019-08-23 2020-08-05 Ethernet interface and related systems, methods and devices

Publications (2)

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JP2022544985A JP2022544985A (ja) 2022-10-24
JPWO2021042110A5 true JPWO2021042110A5 (zh) 2023-08-14

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JP2022510899A Pending JP2022544985A (ja) 2019-08-23 2020-08-05 イーサネットインターフェース、並びに関連するシステム、方法、及びデバイス

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US (1) US11671521B2 (zh)
JP (1) JP2022544985A (zh)
KR (1) KR20220034896A (zh)
CN (1) CN112422219A (zh)
DE (1) DE112020003973T5 (zh)
WO (1) WO2021042110A1 (zh)

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