JPWO2020243355A5 - - Google Patents

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JPWO2020243355A5
JPWO2020243355A5 JP2021571549A JP2021571549A JPWO2020243355A5 JP WO2020243355 A5 JPWO2020243355 A5 JP WO2020243355A5 JP 2021571549 A JP2021571549 A JP 2021571549A JP 2021571549 A JP2021571549 A JP 2021571549A JP WO2020243355 A5 JPWO2020243355 A5 JP WO2020243355A5
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layout
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JP2022534441A (ja
JP7538819B2 (ja
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US201962854848P 2019-05-30 2019-05-30
US62/854,848 2019-05-30
US16/882,217 US20200410153A1 (en) 2019-05-30 2020-05-22 Automated circuit generation
US16/882,217 2020-05-22
PCT/US2020/034987 WO2020243355A1 (en) 2019-05-30 2020-05-28 Automated circuit generation

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JP2022534441A JP2022534441A (ja) 2022-07-29
JPWO2020243355A5 true JPWO2020243355A5 (zh) 2023-06-07
JP7538819B2 JP7538819B2 (ja) 2024-08-22

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US (11) US20200410153A1 (zh)
EP (1) EP3977327A4 (zh)
JP (1) JP7538819B2 (zh)
CN (1) CN113950686A (zh)
SG (1) SG11202112956WA (zh)
TW (2) TWI823003B (zh)
WO (1) WO2020243355A1 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200410153A1 (en) 2019-05-30 2020-12-31 Celera, Inc. Automated circuit generation
KR20210108546A (ko) * 2020-02-25 2021-09-03 삼성전자주식회사 반도체 설계 시뮬레이션을 위한 명령들을 실행하는 컴퓨터 시스템으로 구현된 방법
US20210406661A1 (en) * 2020-06-25 2021-12-30 PolyN Technology Limited Analog Hardware Realization of Neural Networks
US11755808B2 (en) * 2020-07-10 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Mixed poly pitch design solution for power trim
US20220284145A1 (en) * 2021-03-08 2022-09-08 General Electric Company System and method for modeling plant systems utilizing scalable and repeatable modules
CN112906329A (zh) * 2021-03-19 2021-06-04 苏州复鹄电子科技有限公司 一种基于系统级模拟集成电路设计参数自动优化方法
TWI769829B (zh) * 2021-05-21 2022-07-01 崛智科技有限公司 積體電路輔助設計裝置與方法以及電性效能梯度模型建構方法
US20230076736A1 (en) * 2021-08-24 2023-03-09 Cilag Gmbh International Automatic remote center of motion adjustment for robotically controlled uterine manipulator
US12050847B2 (en) * 2022-01-06 2024-07-30 Circuit Mind Limited Computer-implemented circuit schematic design
CN114154451B (zh) * 2022-02-07 2022-06-24 深圳佑驾创新科技有限公司 一种原理图自动绘制方法、装置、设备、介质及产品
CN114611452B (zh) * 2022-03-22 2024-07-02 成都华大九天科技有限公司 基于电路原理图在版图中自动生成Sub Cell的方法
CN114943200B (zh) * 2022-05-26 2023-04-28 清华大学 Mosfet的自动布局方法及装置
CN116090386A (zh) * 2022-12-23 2023-05-09 环鸿电子(昆山)有限公司 模拟电路的自动产生方法及自动产生系统

Family Cites Families (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3001494A (en) 1956-11-05 1961-09-26 Lyon George Albert Method of making wheel covers
US5278769A (en) 1991-04-12 1994-01-11 Lsi Logic Corporation Automatic logic model generation from schematic data base
JPH08227428A (ja) * 1995-02-20 1996-09-03 Matsushita Electric Ind Co Ltd プリント基板cad装置
US5666288A (en) 1995-04-21 1997-09-09 Motorola, Inc. Method and apparatus for designing an integrated circuit
JPH09325980A (ja) 1996-06-06 1997-12-16 Mitsubishi Electric Corp 半導体装置設計システム
JPH10326300A (ja) 1997-05-27 1998-12-08 Mitsubishi Electric Corp 配線板設計装置
JPH11338702A (ja) 1998-05-27 1999-12-10 Toshiba Corp 業務支援装置及び電気システム設計支援装置
US7076415B1 (en) * 1998-12-17 2006-07-11 Cadence Design Systems, Inc. System for mixed signal synthesis
JP2002024301A (ja) 2000-07-06 2002-01-25 Ricoh Co Ltd 部品構成作成編集装置と部品構成作成編集方法と部品構成作成編集処理プログラムを記録したコンピュータ読み取り可能な記録媒体
JP3824203B2 (ja) 2000-03-07 2006-09-20 三菱電機株式会社 電気電子回路の結線図作成装置
US7672827B1 (en) 2000-08-28 2010-03-02 Cadence Design Systems, Inc. Method and system for simulation of analog/digital interfaces with analog tri-state ioputs
JP2002117092A (ja) 2000-10-05 2002-04-19 Fujitsu Ltd 半導体集積回路装置の設計方法、及び設計装置
US6609228B1 (en) * 2000-11-15 2003-08-19 International Business Machines Corporation Latch clustering for power optimization
JP2002163318A (ja) 2000-11-27 2002-06-07 Olympus Optical Co Ltd ハードウェアの共同設計方法
US7058916B2 (en) 2001-06-28 2006-06-06 Cadence Design Systems, Inc. Method for automatically sizing and biasing circuits by means of a database
US7039892B2 (en) 2001-07-24 2006-05-02 Hewlett-Packard Development Company, L.P. Systems and methods for ensuring correct connectivity between circuit designs
US6954921B2 (en) 2002-03-05 2005-10-11 Barcelona Design, Inc. Method and apparatus for automatic analog/mixed signal system design using geometric programming
US20040049370A1 (en) 2002-09-05 2004-03-11 Sun Microsystems, Inc., A Delaware Corporation Self adjusting linear MOSFET simulation techniques
KR100459731B1 (ko) 2002-12-04 2004-12-03 삼성전자주식회사 반도체 집적회로의 시뮬레이션을 위한 인터커넥션 영향을포함한 선택적 연결정보를 생성하는 장치 및 그 방법
JP2004213301A (ja) 2002-12-27 2004-07-29 Renesas Technology Corp 自動回路設計装置およびプログラム
JP4174511B2 (ja) 2003-08-22 2008-11-05 株式会社エイアールテック 半導体集積回路の雑音検出及び測定回路
US7073144B2 (en) 2004-04-15 2006-07-04 International Business Machines Corporation Stability metrics for placement to quantify the stability of placement algorithms
US7257794B2 (en) * 2004-12-17 2007-08-14 Springsoft, Inc. Unit-based layout system for passive IC devices
WO2007149717A2 (en) 2006-06-08 2007-12-27 Lightspeed Logic, Inc. Morphing for global placement using integer linear programming
GB0516634D0 (en) * 2005-08-12 2005-09-21 Univ Sussex Electronic circuit design
US7069527B1 (en) 2005-08-24 2006-06-27 Sun Microsystems, Inc. Algorithm for full-chip resistance extraction
US7418683B1 (en) 2005-09-21 2008-08-26 Cadence Design Systems, Inc Constraint assistant for circuit design
KR20080069647A (ko) 2005-10-26 2008-07-28 엔엑스피 비 브이 집적 회로와 그 테스트 방법 및 장치
JP5224642B2 (ja) * 2005-11-21 2013-07-03 富士通セミコンダクター株式会社 集積回路のレイアウト方法及びコンピュータプログラム
KR100741915B1 (ko) * 2005-12-28 2007-07-24 동부일렉트로닉스 주식회사 더미 금속 채움에 대한 시간 지연 효과를 효율적으로반영할 수 있는 반도체 소자의 설계 방법
US8516418B2 (en) 2006-06-30 2013-08-20 Oracle America, Inc. Application of a relational database in integrated circuit design
US7587694B1 (en) 2006-07-21 2009-09-08 Ciranova, Inc. System and method for utilizing meta-cells
KR100831271B1 (ko) * 2006-08-16 2008-05-22 동부일렉트로닉스 주식회사 물리적 레이어의 프로그램적 생성을 통한 물리적 레이아웃 데이터를 변경하는 방법
US20080109782A1 (en) 2006-10-18 2008-05-08 Utstarcom, Inc. Method and system for pin assignment
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7698678B2 (en) 2007-05-30 2010-04-13 International Business Machines Corporation Methodology for automated design of vertical parallel plate capacitors
JP2009025891A (ja) * 2007-07-17 2009-02-05 Nec Electronics Corp 半導体集積回路の設計方法及び設計プログラム
WO2009020431A1 (en) 2007-08-06 2009-02-12 Teo Swee Ann Method for adapting schematics for different manufacturing processes and different operating specifications
US7917877B2 (en) * 2008-05-09 2011-03-29 Cadence Design Systems, Inc. System and method for circuit schematic generation
US8302059B2 (en) 2008-05-27 2012-10-30 Nxp B.V. Power switch design method and program
TWI369620B (en) 2008-07-30 2012-08-01 Faraday Tech Corp Method and technique for analogue circuit synthesis
US8504953B2 (en) * 2008-10-06 2013-08-06 Mentor Graphics Corporation Schematic generation visualization aid for netlists comprising analog circuits
US8001494B2 (en) 2008-10-13 2011-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Table-based DFM for accurate post-layout analysis
JP2011035210A (ja) 2009-08-03 2011-02-17 Renesas Electronics Corp 半導体集積回路、及び半導体集積回路のレイアウト方法
JP5293488B2 (ja) 2009-08-05 2013-09-18 富士通セミコンダクター株式会社 設計支援プログラム、設計支援装置、および設計支援方法
US8682631B2 (en) 2009-09-03 2014-03-25 Henry Chung-herng Chang Specifications-driven platform for analog, mixed-signal, and radio frequency verification
US8122414B1 (en) 2009-09-29 2012-02-21 Xilinx, Inc. Placeholder-based design flow for creating circuit designs for integrated circuits
US8264065B2 (en) * 2009-10-23 2012-09-11 Synopsys, Inc. ESD/antenna diodes for through-silicon vias
US20120005547A1 (en) 2010-06-30 2012-01-05 Chang Chioumin M Scalable system debugger for prototype debugging
CN102385642B (zh) 2010-09-03 2013-02-13 上海华虹Nec电子有限公司 电阻的器件失配的修正方法
US8789008B2 (en) * 2010-09-13 2014-07-22 Synopsys Taiwan Co., LTD. Methods for generating device layouts by combining an automated device layout generator with a script
US8607019B2 (en) * 2011-02-15 2013-12-10 Shine C. Chung Circuit and method of a memory compiler based on subtractive approach
US8539422B2 (en) 2011-02-24 2013-09-17 Cadence Design Systems, Inc. Method and system for power delivery network analysis
US8453097B2 (en) * 2011-03-22 2013-05-28 Ess Technology, Inc. System and method for series and parallel combinations of electrical elements
US8479136B2 (en) 2011-05-03 2013-07-02 International Business Machines Corporation Decoupling capacitor insertion using hypergraph connectivity analysis
US8464202B2 (en) 2011-05-24 2013-06-11 Lsi Corporation Fully parameterizable representation of a higher level design entity
US8903698B2 (en) * 2012-05-15 2014-12-02 Fujitsu Limited Generating behavioral models for analog circuits
US9026962B2 (en) * 2012-05-30 2015-05-05 Gumstix, Inc. Integrated electronic design automation system
US8850374B2 (en) 2012-11-06 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of reducing parasitic mismatch
US8701055B1 (en) 2012-12-07 2014-04-15 Taiwan Semiconductor Manufacturing Co., Ltd. Macro cell based process design kit for advanced applications
US9183332B2 (en) 2013-04-24 2015-11-10 Bae Systems Information And Electronic Systems Integration Inc. Method for simulation of partial VLSI ASIC design
ITTO20130575A1 (it) * 2013-07-09 2015-01-10 St Microelectronics Srl Procedimento per la progettazione automatica di un circuito elettronico, relativo sistema e prodotto informatico
US9619605B1 (en) * 2013-07-24 2017-04-11 Cadence Design Systems, Inc. System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects
US9158878B2 (en) 2013-08-23 2015-10-13 Kabushiki Kaisha Toshiba Method and apparatus for generating circuit layout using design model and specification
CN103532554B (zh) 2013-10-23 2016-04-27 中国电子科技集团公司第二十四研究所 电容阵列及其版图设计方法
US9268895B2 (en) * 2013-11-06 2016-02-23 Texas Instruments Incorporated Circuit design synthesis tool with export to a computer-aided design format
US9753895B2 (en) * 2014-02-28 2017-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method for process variation analysis of an integrated circuit
US20150269297A1 (en) 2014-03-19 2015-09-24 G-Analog Design Automation Limited Methods for reducing post layout circuit simulation results
US9342647B2 (en) 2014-03-21 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design method and apparatus
CN105447222B (zh) * 2014-09-22 2018-09-25 台湾积体电路制造股份有限公司 用于集成电路的工艺变化分析的方法
US9984133B2 (en) * 2014-10-16 2018-05-29 Palantir Technologies Inc. Schematic and database linking system
US9494651B2 (en) 2015-01-08 2016-11-15 Honeywell Limited Method for testing embedded systems
US9672308B1 (en) * 2015-03-11 2017-06-06 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing three-dimensional operations for electronic designs
US9779193B1 (en) 2015-03-31 2017-10-03 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations
US10783292B1 (en) 2015-05-21 2020-09-22 Pulsic Limited Automated analog layout
US20160350061A1 (en) * 2015-05-29 2016-12-01 Qualcomm Incorporated Remote rendering from a source device to a sink device
KR102180404B1 (ko) * 2015-06-02 2020-11-18 삼성전자주식회사 사용자 단말 장치 및 그 제어 방법
US20170061313A1 (en) 2015-09-02 2017-03-02 Infineon Technologies Ag System and Method for Estimating a Performance Metric
US9613173B1 (en) 2015-10-01 2017-04-04 Xilinx, Inc. Interactive multi-step physical synthesis
US9842178B2 (en) 2015-10-29 2017-12-12 Cadence Design Systems, Inc. Systems and methods for binding mismatched schematic and layout design hierarchy
US10437953B2 (en) 2016-07-08 2019-10-08 efabless corporation Systems for engineering integrated circuit design and development
ES2978110T3 (es) 2016-07-27 2024-09-05 Fraunhofer Ges Forschung Aparato y método para generar elementos MOS en serie y aparato y método para generar una disposición de circuito a partir de un esquema de circuito de transistor MOS
WO2018057454A1 (en) * 2016-09-20 2018-03-29 Octavo Systems Llc Method for routing bond wires in system in a package (sip) devices
US10285276B1 (en) 2016-09-23 2019-05-07 Cadence Design Systems, Inc. Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell
US10289793B1 (en) 2017-02-28 2019-05-14 Cadence Design Systems, Inc. System and method to generate schematics from layout-fabrics with a common cross-fabric model
US10063159B1 (en) * 2017-06-30 2018-08-28 Dialog Semiconductor Inc. Adaptive synchronous rectifier sensing deglitch
US20190042684A1 (en) 2017-08-02 2019-02-07 Oracle International Corporation Schematic Driven Analog Circuit Layout Automation
CN107679262B (zh) 2017-08-11 2021-03-26 上海集成电路研发中心有限公司 一种mos器件衬底外围寄生电阻的建模方法
US10558780B1 (en) 2017-09-30 2020-02-11 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design
US10572618B2 (en) * 2017-11-28 2020-02-25 International Business Machines Corporation Enabling automatic staging for nets or net groups with VHDL attributes
US10657218B2 (en) 2017-11-29 2020-05-19 Arm Limited Wirelength distribution schemes and techniques
US10770160B2 (en) 2017-11-30 2020-09-08 Attopsemi Technology Co., Ltd Programmable resistive memory formed by bit slices from a standard cell library
US10808333B2 (en) * 2018-01-08 2020-10-20 Totic Technology Inc. Method and apparatus for performing layout designs using stem cells
US10796059B2 (en) 2018-03-22 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout generation method and system
US10846456B2 (en) 2018-05-02 2020-11-24 Taiwan Semiconductor Manufacturing Company Ltd. Integrated circuit modeling methods and systems
US10783296B1 (en) 2018-06-08 2020-09-22 Diakopto, Inc. Matched net and device analysis based on parasitics
US10699051B1 (en) 2018-06-29 2020-06-30 Cadence Design Systems, Inc. Method and system for performing cross-validation for model-based layout recommendations
US10885258B1 (en) 2018-09-25 2021-01-05 Synopsys, Inc. Fixing ESD path resistance errors in circuit design layout
US11281560B2 (en) * 2019-03-19 2022-03-22 Microsoft Technology Licensing, Llc Input/output data transformations when emulating non-traced code with a recorded execution of traced code
US20200410153A1 (en) 2019-05-30 2020-12-31 Celera, Inc. Automated circuit generation
US20230076736A1 (en) 2021-08-24 2023-03-09 Cilag Gmbh International Automatic remote center of motion adjustment for robotically controlled uterine manipulator

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