JPWO2019166925A1 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JPWO2019166925A1 JPWO2019166925A1 JP2020503104A JP2020503104A JPWO2019166925A1 JP WO2019166925 A1 JPWO2019166925 A1 JP WO2019166925A1 JP 2020503104 A JP2020503104 A JP 2020503104A JP 2020503104 A JP2020503104 A JP 2020503104A JP WO2019166925 A1 JPWO2019166925 A1 JP WO2019166925A1
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- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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Abstract
Description
本実施の形態では、本発明の一態様の半導体装置、表示装置、およびその作製方法について説明する。
図1(A)は、トランジスタ100の上面図であり、図1(B)は、図1(A)に示す一点鎖線A1−A2における切断面の断面図に相当し、図1(C)は、図1(A)に示す一点鎖線B1−B2における切断面の断面図に相当する。なお、図1(A)において、トランジスタ100の構成要素の一部(ゲート絶縁層等)を省略して図示している。また、一点鎖線A1−A2方向はチャネル長方向、一点鎖線B1−B2方向はチャネル幅方向に相当する。また、トランジスタの上面図については、以降の図面においても図1(A)と同様に、構成要素の一部を省略して図示するものとする。
以下では、上記構成例1と一部の構成が異なるトランジスタの構成例について説明する。
以下では、上記構成例2と一部の構成が異なるトランジスタの構成例について説明する。なお、以下では、上記構成例2と重複する部分は説明を省略する場合がある。また、以下で示す図面において、上記構成例2と同様の機能を有する部分についてはハッチングパターンを同じくし、符号を付さない場合もある。
以下では、不純物を含む半導体膜を容量素子の一方の電極として用い、トランジスタと容量素子とを同一面上に形成する例について説明する。
次に、本実施の形態の半導体装置に含まれる構成要素について、詳細に説明する。
基板102の材質などに大きな制限はないが、少なくとも、後の熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。
絶縁層103としては、スパッタリング法、CVD法、蒸着法、パルスレーザー堆積(PLD)法等を適宜用いて形成することができる。また、絶縁層103としては、例えば、酸化物絶縁膜または窒化物絶縁膜を単層または積層して形成することができる。なお、半導体層108との界面特性を向上させるため、絶縁層103において少なくとも半導体層108と接する領域は酸化物絶縁膜で形成することが好ましい。また、絶縁層103には、加熱により酸素を放出する膜を用いることが好ましい。
ゲート電極として機能する導電層112及び導電層106、ソース電極として機能する導電層120a、ドレイン電極として機能する導電層120bとしては、クロム、銅、アルミニウム、金、銀、亜鉛、モリブデン、タンタル、チタン、タングステン、マンガン、ニッケル、鉄、コバルトから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いてそれぞれ形成することができる。
トランジスタ100等のゲート絶縁膜として機能する絶縁層110は、PECVD法、スパッタリング法等により形成できる。絶縁層110としては、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁層を用いることができる。なお、絶縁層110を、2層の積層構造または3層以上の積層構造としてもよい。
半導体層108がIn−M−Zn酸化物の場合、In−M−Zn酸化物を成膜するために用いるスパッタリングターゲットは、Inの原子数比がMの原子数比以上であることが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、In:M:Zn=1:1:1、In:M:Zn=1:1:1.2、In:M:Zn=2:1:3、In:M:Zn=3:1:2、In:M:Zn=4:2:4.1、In:M:Zn=5:1:6、In:M:Zn=5:1:7、In:M:Zn=5:1:8、In:M:Zn=6:1:6、In:M:Zn=5:2:5等が挙げられる。
以下では、本発明の一態様のトランジスタの作製方法の例について説明する。ここでは、構成例2で例示したトランジスタ100を例に挙げて説明する。
基板102上に導電膜を成膜し、これをエッチングにより加工して、ゲート電極として機能する導電層106を形成する。
続いて、絶縁層103を成膜する前に、領域106dには、酸素を含むガスと、還元性を有するガスの混合ガスを用いたプラズヤ処理150を行う(図5(A))。領域106dにプラズマ処理を行うことで、続いて行われる絶縁層103の成膜工程において領域106dの酸化が抑制される。当該プラズマ処理は、導電層112のプラズマ処理と同じプラズマ処理が行われる。当該プラズマ処理は、導電層112のプラズマ処理の項にて詳細に説明する。
続いて、基板102、導電層106を覆って絶縁層103を形成する。絶縁層103はPECVD法、ALD法、スパッタリング法などを用いて形成することができる。なお、絶縁層103の形成は、該プラズマ処理150と同一の処理室で処理されることが好ましい。さらに、絶縁層103の成膜処理は、該プラズマ処理と同じ温度で行われることが好ましい。
続いて、絶縁層103上に金属酸化物膜を成膜し、これを加工することにより島状の半導体層108を形成する(図5(B))。
続いて、絶縁層103及び半導体層108を覆って、絶縁層110と金属酸化物膜114fを積層して成膜する(図5(C))。
続いて、金属酸化物膜114f上に、導電層112となる導電膜112fを成膜する(図5(D))。導電膜112fは、金属または合金のスパッタリングターゲットを用いたスパッタリング法により成膜することが好ましい。
続いて、導電層112をマスクとして、絶縁層110及び半導体層108に不純物元素140を供給(添加、または注入ともいう)する処理を行い、領域108n、領域110d、及び領域103dを形成する(図6(A))。半導体層108及び絶縁層110のうち、導電層112と重畳する領域には、導電層112がマスクとなり不純物元素140は供給されない。
続いて、絶縁層110を成膜する前に、領域112dには、酸素を含むガスと、還元性を有するガスの混合ガスを用いたプラズマ処理150を行う(図6(B))。領域112dにプラズマ処理を行うことで、続いて行われる絶縁層116の成膜工程において領域112dの酸化が抑制される。
続いて、絶縁層116及び絶縁層118を順に形成する(図6(C))。絶縁層116は、上記プラズマ処理後の導電層112を大気に暴露することなく連続して成膜することが好ましい。絶縁層116の成膜は、プラズマ化学気相堆積(プラズマCVD)法を用いて行うことが好ましい。このとき、プラズマ処理と絶縁層116の成膜を、同じ装置内の同じ成膜室内で、連続して行うことが好ましい。また、プラズマ処理と絶縁層116の成膜を、同じ温度で行うことが好ましい。
絶縁層116または絶縁層118の形成後、加熱処理を行う。加熱処理は、窒素、酸素、希ガスのうち一以上を含む雰囲気下にて、150℃以上450℃以下、好ましくは200℃以上400℃以下の温度で行うことが好ましい。当該加熱処理により、より安定して低抵抗な領域108nとすることができる。例えば、上記温度で加熱処理を行うことにより、不純物元素140を適度に拡散して局所的に均一化され、理想的な不純物元素の濃度勾配を有する領域108n及び領域110dが形成されうる。なお、加熱処理の温度が高すぎる(例えば500℃以上)と、不純物元素140がチャネル形成領域内にまで拡散し、トランジスタの電気特性や信頼性の悪化を招く恐れがある。また、導電層106の領域106d、または導電層112の領域112dは、加熱処理を行っても酸化が抑制されることが好ましい。
続いて、絶縁層118の所望の位置にリソグラフィによりマスクを形成した後、絶縁層118、絶縁層116、及び絶縁層110の一部をエッチングすることで、領域108nに達する開口部141a及び開口部141bを形成する。
続いて、開口部141a及び開口部141bを覆うように、絶縁層118上に導電膜を成膜し、当該導電膜を所望の形状に加工することで、導電層120a及び導電層120bを形成する(図6(D))。
本実施の形態では、先の実施の形態で例示したトランジスタを有する表示装置の一例について説明を行う。
図7(A)に、表示装置700の上面図を示す。表示装置700は、シール材712により貼りあわされた第1の基板701と第2の基板705を有する。また第1の基板701、第2の基板705、及びシール材712で封止される領域において、第1の基板701上に画素部702、ソースドライバ回路部704、及びゲートドライバ回路部706が設けられる。また画素部702には、複数の表示素子が設けられる。
以下では、表示素子として液晶素子及びEL素子を用いる構成について、図8乃至図10を用いて説明する。なお、図8乃至図10は、それぞれ図7(A)に示す一点鎖線Q−Rにおける断面図である。図8及び図9は、表示素子として液晶素子を用いた構成であり、図10は、EL素子を用いた構成である。
図8乃至図10に示す表示装置700は、引き回し配線部711と、画素部702と、ソースドライバ回路部704と、FPC端子部708と、を有する。引き回し配線部711は、信号線710を有する。画素部702は、トランジスタ750及び容量素子790を有する。ソースドライバ回路部704は、トランジスタ752を有する。図9では、容量素子790が無い場合を示している。
図8に示す表示装置700は、液晶素子775を有する。液晶素子775は、導電層772、導電層774、及びこれらの間に液晶層776を有する。導電層774は、第2の基板705側に設けられ、共通電極としての機能を有する。また、導電層772は、トランジスタ750が有するソース電極またはドレイン電極と電気的に接続される。導電層772は、平坦化絶縁膜770上に形成され、画素電極として機能する。
図10に示す表示装置700は、発光素子782を有する。発光素子782は、導電層772、EL層786、及び導電膜788を有する。EL層786は、有機化合物、または量子ドットなどの無機化合物を有する。
また、図8乃至図10に示す表示装置700に入力装置を設けてもよい。当該入力装置としては、例えば、タッチセンサ等が挙げられる。
本実施の形態では、本発明の一態様の半導体装置を有する表示装置について、図11を用いて説明を行う。
以下では、画素に表示される階調を補正するためのメモリを備える画素回路と、これを有する表示装置について説明する。実施の形態1で例示したトランジスタは、以下で例示する画素回路に用いられるトランジスタに適用することができる。
図12(A)に、画素回路400の回路図を示す。画素回路400は、トランジスタM1、トランジスタM2、容量C1、及び回路401を有する。また画素回路400には、配線S1、配線S2、配線G1、及び配線G2が接続される。
続いて、図12(B)を用いて、画素回路400の動作方法の一例を説明する。図12(B)は、画素回路400の動作に係るタイミングチャートである。なおここでは説明を容易にするため、配線抵抗などの各種抵抗や、トランジスタや配線などの寄生容量、及びトランジスタのしきい値電圧などの影響は考慮しない。
期間T1では、配線G1と配線G2の両方に、トランジスタをオン状態にする電位を与える。また、配線S1には固定電位である電位Vrefを供給し、配線S2には第1データ電位Vwを供給する。
続いて期間T2では、配線G1にはトランジスタM1をオン状態とする電位を与え、配線G2にはトランジスタM2をオフ状態とする電位を与える。また、配線S1には第2データ電位Vdataを供給する。配線S2には所定の定電位を与える、またはフローティング状態としてもよい。
〔液晶素子を用いた例〕
図12(C)に示す画素回路400LCは、回路401LCを有する。回路401LCは、液晶素子LCと、容量C2とを有する。
図12(D)に示す画素回路400ELは、回路401ELを有する。回路401ELは、発光素子EL、トランジスタM3、及び容量C2を有する。
本実施の形態では、本発明の一態様を用いて作製することができる表示モジュールについて説明する。
本実施の形態では、本発明の一態様を用いて作製された表示装置を備える電子機器について説明する。
Claims (7)
- 金属酸化物を含む半導体層を形成する第1の工程と、
前記半導体層を覆って、第1の絶縁層を形成する第2の工程と、
前記第1の絶縁層上に、第1の導電膜を成膜する第3の工程と、
前記第1の導電膜の一部をエッチングすることで第1の導電層を形成し、前記半導体層上に前記第1の導電層が重なる第1の領域と、前記半導体層上に前記第1の導電層が重ならない第2の領域とを形成する第4の工程と、
前記第1の導電層に対して、第1の処理を行う第5の工程と、
前記第1の導電層に接して、酸化物を含む第2の絶縁層を成膜する第6の工程と、を有し、
前記第1の導電層は、銅、銀、金、またはアルミニウムを含み、
前記第1の処理は、酸素元素を含み、水素元素を含まない第1のガスと、水素元素を含み、酸素元素を含まない第2のガスとの混合ガスを含む雰囲気下における、プラズマ処理であり、
前記第2の絶縁層は、前記第1のガスと、シリコン元素を含む第3のガスとを含む成膜ガスを用いたプラズマ化学気相堆積法により形成され、
前記第6の工程は、前記第5の工程の後に大気暴露することなく連続して行われる、
半導体装置の作製方法。 - 金属酸化物を含む半導体層を形成する第1の工程と、
前記半導体層を覆って、第1の絶縁層を形成する第2の工程と、
前記第1の絶縁層上に、順に第1の金属酸化物膜及び第1の導電膜を成膜する第3の工程と、
前記第1の導電膜及び前記第1の金属酸化物膜の一部をエッチングすることで第1の導電層及び第1の金属酸化物層を形成し、前記半導体層上に前記第1の導電層が重なる第1の領域と、前記半導体層上に前記第1の導電層が重ならない第2の領域とを形成する第4の工程と、
前記第1の導電層に対して、第1の処理を行う第5の工程と、
前記第1の導電層に接して、酸化物を含む第2の絶縁層を成膜する第6の工程と、を有し、
前記第1の導電層は、銅、銀、金、またはアルミニウムを含み、
前記第1の処理は、酸素元素を含み、水素元素を含まない第1のガスと、水素元素を含み、酸素元素を含まない第2のガスとの混合ガスを含む雰囲気下における、プラズマ処理であり、
前記第2の絶縁層は、前記第1のガスと、シリコン元素を含む第3のガスとを含む成膜ガスを用いたプラズマ化学気相堆積法により形成され、
前記第6の工程は、前記第5の工程の後に大気暴露することなく連続して行われる、
半導体装置の作製方法。 - 請求項1又は請求項2において、
前記第5の工程において、前記第1の処理は、処理室に供給される前記第1のガスと前記第2のガスの流量を、前記第1のガスの流量を100%としたとき、前記第2のガスの流量が0.5%以上100%以下となるように制御して行われる、
半導体装置の作製方法。 - 請求項1乃至請求項3のいずれか一において、
前記第1のガスは、N2OまたはO2を含み、
前記第2のガスは、NH3またはH2を含む、
半導体装置の作製方法。 - 請求項1乃至請求項4のいずれか一において、
前記第5の工程と前記第6の工程とは、同一の処理室で、且つ同じ温度で行われる、
半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一において、
前記第1の工程において、前記半導体層は、第2の金属酸化物膜と、第3の金属酸化物膜とを順に成膜した後に、当該第2の金属酸化物層と当該第3の金属酸化物層とをエッチングして加工することにより形成し、
前記第3の金属酸化物層は、前記第2の金属酸化物層より結晶性が高くなるように形成する、
半導体装置の作製方法。 - 請求項1乃至請求項6のいずれか一において、
前記第1の工程より前に、第1の導電層を形成する第7の工程と、
前記第7の工程と前記第1の工程の間に、前記第1の導電層を覆って第3の絶縁層を形成する第8の工程と、を有し、
前記第1の工程において、前記半導体層は、前記第1の導電層と重畳するように形成する、
半導体装置の作製方法。
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