JPWO2019123109A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019123109A1 JPWO2019123109A1 JP2019560506A JP2019560506A JPWO2019123109A1 JP WO2019123109 A1 JPWO2019123109 A1 JP WO2019123109A1 JP 2019560506 A JP2019560506 A JP 2019560506A JP 2019560506 A JP2019560506 A JP 2019560506A JP WO2019123109 A1 JPWO2019123109 A1 JP WO2019123109A1
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Images
Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
Description
本実施の形態では、本発明の一態様の半導体装置、表示装置、およびその作製方法について説明する。
図1(A)は、トランジスタ100の上面図であり、図1(B)は、図1(A)に示す一点鎖線A1−A2における切断面の断面図に相当し、図1(C)は、図1(A)に示す一点鎖線B1−B2における切断面の断面図に相当する。なお、図1(A)において、トランジスタ100の構成要素の一部(ゲート絶縁層等)を省略して図示している。また、一点鎖線A1−A2方向はチャネル長方向、一点鎖線B1−B2方向はチャネル幅方向に相当する。また、トランジスタの上面図については、以降の図面においても図1(A)と同様に、構成要素の一部を省略して図示する。
以下では、上記構成例1と一部の構成が異なるトランジスタの構成例について説明する。なお、以下では、上記構成例1と重複する部分は説明を省略する場合がある。また、以下で示す図面において、上記構成例と同様の機能を有する部分についてはハッチングパターンを同じくし、符号を付さない場合もある。
以下では、構成例2の変形例について説明する。
図3(A)、(B)、(C)に示すトランジスタ100Bは、絶縁層104を導電層112と同じフォトマスクを用いて加工した場合の例である。
図4(A)に示すチャネル幅方向の断面は、絶縁層104のチャネル幅方向の長さが異なる点で、図2(C)と主に相違している。
図4(B)は、絶縁層104のチャネル幅方向の端部が、導電層112のチャネル幅方向の端部、及び導電層106のチャネル幅方向の端部よりも内側に位置し、且つ、開口部142が設けられる部分に絶縁層104が位置している例である。
図4(C)は、絶縁層104のチャネル幅方向の端部が、導電層112のチャネル幅方向の端部、及び導電層106のチャネル幅方向の端部よりも外側に位置している例である。
以下では、上記トランジスタを表示装置の画素に適用する場合の例について説明する。
次に、本実施の形態の半導体装置に含まれる構成要素について、詳細に説明する。
基板102の材質などに大きな制限はないが、少なくとも、後の熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。
絶縁層104としては、スパッタリング法、CVD法、蒸着法、パルスレーザー堆積(PLD)法等を適宜用いて形成することができる。また、絶縁層104としては、例えば、酸化物絶縁膜または窒化物絶縁膜を単層または積層して形成することができる。なお、半導体層108との界面特性を向上させるため、絶縁層104において少なくとも半導体層108と接する領域は酸化物絶縁膜で形成することが好ましい。また、絶縁層104には、加熱により酸素を放出する膜を用いることが好ましい。
ゲート電極として機能する導電層112及び導電層106、ソース電極として機能する導電層120a、ドレイン電極として機能する導電層120bとしては、クロム、銅、アルミニウム、金、銀、亜鉛、モリブデン、タンタル、チタン、タングステン、マンガン、ニッケル、鉄、コバルトから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いてそれぞれ形成することができる。
トランジスタ100等のゲート絶縁膜として機能する絶縁層110は、PECVD法、スパッタリング法等により形成できる。絶縁層110としては、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁層を用いることができる。なお、絶縁層110を、2層の積層構造または3層以上の積層構造としてもよい。
半導体層108がIn−M−Zn酸化物の場合、In−M−Zn酸化物を成膜するために用いるスパッタリングターゲットは、Inの原子数比がMの原子数比以上であることが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、In:M:Zn=1:1:1、In:M:Zn=1:1:1.2、In:M:Zn=2:1:3、In:M:Zn=3:1:2、In:M:Zn=4:2:4.1、In:M:Zn=5:1:6、In:M:Zn=5:1:7、In:M:Zn=5:1:8、In:M:Zn=6:1:6、In:M:Zn=5:2:5等が挙げられる。
以下では、本発明の一態様のトランジスタの作製方法の例について説明する。ここでは、構成例2で例示したトランジスタ100Aを例に挙げて説明する。
基板102上に導電膜を成膜し、これをエッチングにより加工して、ゲート電極として機能する導電層106を形成する(図6(A))。
続いて、基板102、導電層106を覆って絶縁層103と絶縁膜104fを積層して形成する(図6(B))。絶縁層103及び絶縁膜104fはそれぞれ、PECVD法、ALD法、スパッタリング法などを用いて形成することができる。
続いて、絶縁層104及び絶縁層103上に金属酸化物膜を成膜し、これを加工することにより半導体層108を形成する(図7(A))。
続いて、絶縁層103、絶縁層104、及び半導体層108を覆って、絶縁層110となる絶縁膜110fと、金属酸化物層114となる金属酸化物膜114fを積層して成膜する。
続いて、金属酸化物膜114f上に、導電層112となる導電膜を成膜する。当該導電膜は、金属または合金のスパッタリングターゲットを用いたスパッタリング法により成膜することが好ましい。
続いて、絶縁層104、半導体層108、絶縁層110の側面、金属酸化物層114の側面、及び導電層112等を覆って、絶縁層116を形成する。またこのとき、半導体層108及び絶縁層104の端部よりも外側において、絶縁層103と絶縁層116とが接する領域が形成される(図8(A))。
続いて、加熱処理を行うことが好ましい。加熱処理により、半導体層108の領域108nの低抵抗化をより促進させることができる。
続いて、絶縁層116を覆って絶縁層118を形成する。絶縁層118は、例えばPECVD法により形成することができる。
続いて、絶縁層118及び絶縁層116の一部をエッチングすることで、領域108nに達する開口部141a、開口部141bを形成する。
続いて、開口部141a、開口部141bを覆うように、絶縁層118上に導電膜を成膜し、当該導電膜を所望の形状に加工することで、導電層120a、導電層120bを形成する(図8(B))。
本実施の形態では、先の実施の形態で例示したトランジスタを有する表示装置の一例について説明を行う。
図9(A)に、表示装置700の上面図を示す。表示装置700は、シール材712により貼りあわされた第1の基板701と第2の基板705を有する。また第1の基板701、第2の基板705、及びシール材712で封止される領域において、第1の基板701上に画素部702、ソースドライバ回路部704、及びゲートドライバ回路部706が設けられる。また画素部702には、複数の表示素子が設けられる。
以下では、表示素子として液晶素子及びEL素子を用いる構成について、図10乃至図12を用いて説明する。なお、図10乃至図12は、それぞれ図9(A)に示す一点鎖線Q−Rにおける断面図である。図10及び図11は、表示素子として液晶素子を用いた構成であり、図12は、EL素子を用いた構成である。
図10乃至図12に示す表示装置700は、引き回し配線部711と、画素部702と、ソースドライバ回路部704と、FPC端子部708と、を有する。引き回し配線部711は、信号線710を有する。画素部702は、トランジスタ750及び容量素子790を有する。ソースドライバ回路部704は、トランジスタ752を有する。
図10に示す表示装置700は、液晶素子775を有する。液晶素子775は、導電膜772、導電膜774、及びこれらの間に液晶層776を有する。導電膜774は、第2の基板705側に設けられ、共通電極としての機能を有する。また、導電膜772は、トランジスタ750が有するソース電極またはドレイン電極と電気的に接続される。導電膜772は、平坦化絶縁膜770上に形成され、画素電極として機能する。
図12に示す表示装置700は、発光素子782を有する。発光素子782は、導電膜772、EL層786、及び導電膜788を有する。EL層786は、有機化合物、または量子ドットなどの無機化合物を有する。
また、図10乃至図12に示す表示装置700に入力装置を設けてもよい。当該入力装置としては、例えば、タッチセンサ等が挙げられる。
本実施の形態では、本発明の一態様の半導体装置を有する表示装置について、図13を用いて説明を行う。
以下では、画素に表示される階調を補正するためのメモリを備える画素回路と、これを有する表示装置について説明する。実施の形態1で例示したトランジスタは、以下で例示する画素回路に用いられるトランジスタに適用することができる。
図14(A)に、画素回路400の回路図を示す。画素回路400は、トランジスタM1、トランジスタM2、容量C1、及び回路401を有する。また画素回路400には、配線S1、配線S2、配線G1、及び配線G2が接続される。
続いて、図14(B)を用いて、画素回路400の動作方法の一例を説明する。図14(B)は、画素回路400の動作に係るタイミングチャートである。なおここでは説明を容易にするため、配線抵抗などの各種抵抗や、トランジスタや配線などの寄生容量、及びトランジスタのしきい値電圧などの影響は考慮しない。
期間T1では、配線G1と配線G2の両方に、トランジスタをオン状態にする電位を与える。また、配線S1には固定電位である電位Vrefを供給し、配線S2には第1データ電位Vwを供給する。
続いて期間T2では、配線G1にはトランジスタM1をオン状態とする電位を与え、配線G2にはトランジスタM2をオフ状態とする電位を与える。また、配線S1には第2データ電位Vdataを供給する。配線S2には所定の定電位を与える、またはフローティング状態としてもよい。
〔液晶素子を用いた例〕
図14(C)に示す画素回路400LCは、回路401LCを有する。回路401LCは、液晶素子LCと、容量C2とを有する。
図14(D)に示す画素回路400ELは、回路401ELを有する。回路401ELは、発光素子EL、トランジスタM3、及び容量C2を有する。
本実施の形態では、本発明の一態様を用いて作製することができる表示モジュールについて説明する。
本実施の形態では、本発明の一態様を用いて作製された表示装置を備える電子機器について説明する。
作製したトランジスタの構成は、実施の形態1及び図3で例示したトランジスタ100Bを援用できる。また、比較として絶縁層104に対応する酸化物膜を加工しないトランジスタも作製した。
上記で作製した試料Aと比較試料について、Id−Vg特性を測定した。測定したトランジスタのサイズは、チャネル長を約3μm、チャネル幅を約3μmである。また測定数は20とした。
Claims (9)
- 第1の絶縁層と、第2の絶縁層と、第3の絶縁層と、半導体層と、第1の導電層と、を有し、
前記第2の絶縁層は、前記第1の絶縁層上に位置し、且つ島状の形状を有し、
前記半導体層は、前記第2の絶縁層の上面に接する部分と、前記第1の絶縁層の上面に接する部分と、を有し、且つ島状の形状を有し、
前記第3の絶縁層および前記第1の導電層は、前記半導体層上に、この順に積層して設けられ、
前記第2の絶縁層は、少なくとも前記第1の導電層と前記半導体層とが重なる領域に設けられ、
チャネル長方向において、前記半導体層は、前記第2の絶縁層の一対の端部を越えて外側に延在し、
チャネル幅方向において、前記半導体層は、前記第2の絶縁層の一対の端部よりも内側に位置し、
前記半導体層は、金属酸化物を含み、
前記第1の絶縁層は、金属酸化物、または窒化物を含み、
前記第2の絶縁層及び前記第3の絶縁層は、酸化物を含む、
半導体装置。 - 請求項1において、
第2の導電層および第3の導電層を有し、
前記第2の導電層及び前記第3の導電層は、前記第2の絶縁層を挟んで、互いに離間して設けられ、
前記第2の導電層及び前記第3の導電層は、それぞれ前記第2の絶縁層が設けられない領域において、前記半導体層と接する、
半導体装置。 - 請求項1または請求項2において、
第4の絶縁層を有し、
前記第4の絶縁層は、前記第2の絶縁層、前記半導体層、前記第3の絶縁層、及び前記第1の導電層を覆い、前記第2の絶縁層が設けられない領域において前記半導体層の上面の一部と接する部分を有し、且つ、前記半導体層の端部よりも外側において前記第1の絶縁層と接する部分を有し、
前記第4の絶縁層は、金属酸化物、または窒化物を含む、
半導体装置。 - 請求項3において、
前記第4の絶縁層は、窒化シリコン、または窒化アルミニウムを含む、
半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第1の絶縁層は、窒化シリコン、または酸化アルミニウムを含む、
半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記第1の絶縁層よりも下に第4の導電層を有し、
前記第4の導電層は、前記半導体層、前記第1の導電層、及び前記第2の絶縁層の全てと重なる領域を有する、
半導体装置。 - 請求項6において、
前記半導体層が設けられない領域であって、前記第2の導電層と前記第4の導電層とが重畳する領域に、第5の絶縁層を有し、
前記第5の絶縁層は、前記第2の絶縁層と同一面上に位置し、且つ前記第2の絶縁層と同一の材料を含む、
半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記第3の絶縁層と、前記第1の導電層との間に、金属酸化物層を有し、
前記金属酸化物層と、前記半導体層とは、同じ金属元素を含む、
半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記第3の絶縁層と、前記第1の導電層との間に、金属酸化物層を有し、
前記金属酸化物層は、アルミニウムまたはハフニウムを含む、
半導体装置。
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