JPWO2016039073A1 - 半導体装置および半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000002344 surface layer Substances 0.000 claims abstract description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 47
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 47
- 239000011229 interlayer Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 238000003763 carbonization Methods 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 39
- 239000010936 titanium Substances 0.000 description 27
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000005245 sintering Methods 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 239000012535 impurity Substances 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
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Abstract
Description
図1は、本発明の半導体装置の実施例1におけるMOSFETの断面構造図である。なお、本実施例では第1導電型をN型、第2導電型をP型としているがこれを逆に形成することも可能である。
図7は、本発明の半導体装置の実施例2におけるMOSFETの断面構造図である。実施例2が実施例1と異なる点は、第3のバリア膜32を第1のソース電極9の上にも形成した点である。これは、第1のソース電極9のNiがソースコンタクト層内、層間絶縁膜8に接触せずに形成され、シンタリング時のNiの染み込みが無い場合に適用でき、第3のバリア膜32をソースコンタクト部分に形成することで応力によるTiNのクラック発生を抑制し素子の信頼性を向上させることができる。
2 N型炭化珪素層
3 P型領域
4 N型ソース領域
5 P型コンタクト領域
6 ゲート絶縁膜
7 第1のゲート電極
8 層間絶縁膜
9 第1のソース電極
10 第1のバリア膜
11 第2のソース電極
12 ドレイン電極
21 酸化膜
22 第2のゲート電極
23 第2のゲート金属電極
31 第2のバリア膜
32 第3のバリア膜
Claims (3)
- 第1導電型炭化珪素基板と、前記第1導電型炭化珪素基板のおもて面側に形成される低濃度の第1導電型炭化珪素層と、前記第1導電型炭化珪素層の表面層に選択的に形成された第2導電型領域と、前記第2導電型領域内に形成された第1導電型ソース領域と高濃度の第2導電型コンタクト領域と、前記第2導電型領域の、前記第1導電型炭化珪素層と前記第1導電型ソース領域との間の領域に接して設けられたゲート絶縁膜と、前記ゲート絶縁膜を挟んで前記第2導電型領域の反対側に設けられたゲート電極と、前記ゲート電極を覆う層間絶縁膜と、前記第2導電型コンタクト領域および前記第1導電型ソース領域の表面に電気的に接続するソース電極と、前記第1導電型炭化珪素基板の裏面側に形成されたドレイン電極と、を備え、
前記層間絶縁膜を覆う第1のバリア膜と、ゲートコンタクトホール部分に設けた第2のバリア膜とを有し、前記第1のバリア膜と前記第2のバリア膜上に、それぞれ金属電極が形成されていることを特徴とする半導体装置。 - 前記第1のバリア膜および前記第2のバリア膜は、TiN又はTiとTiNの積層構造からなり、かつその表面がTiで覆われたことを特徴とする請求項1に記載の半導体装置。
- 第1導電型炭化珪素基板と、前記第1導電型炭化珪素基板のおもて面側に形成される低濃度の第1導電型炭化珪素層と、前記第1導電型炭化珪素層の表面層に選択的に形成された第2導電型領域と、前記第2導電型領域内に形成された第1導電型ソース領域と高濃度の第2導電型コンタクト領域と、前記第2導電型領域の、前記第1導電型炭化珪素層と前記第1導電型ソース領域との間の領域に接して設けられたゲート絶縁膜と、前記ゲート絶縁膜を挟んで前記第2導電型領域の反対側に設けられたゲート電極と、前記ゲート電極を覆う層間絶縁膜と、前記第2導電型コンタクト領域および前記第1導電型ソース領域の表面に電気的に接続するソース電極と、前記第1導電型炭化珪素基板の裏面側に形成されたドレイン電極と、を備えた半導体装置の製造方法において、
前記ソース電極をNiシリサイド層で形成する工程と、
ソースコンタクトホールとゲートコンタクトホールを同時に形成する工程と、
前記ゲートコンタクトホールをTiN又はTiとTiNの積層構造からなるバリア膜で覆う工程と、
を含むことを特徴とする半導体装置の製造方法。
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