JPWO2013073591A1 - デカップリング回路及び半導体集積回路 - Google Patents
デカップリング回路及び半導体集積回路 Download PDFInfo
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- JPWO2013073591A1 JPWO2013073591A1 JP2013544305A JP2013544305A JPWO2013073591A1 JP WO2013073591 A1 JPWO2013073591 A1 JP WO2013073591A1 JP 2013544305 A JP2013544305 A JP 2013544305A JP 2013544305 A JP2013544305 A JP 2013544305A JP WO2013073591 A1 JPWO2013073591 A1 JP WO2013073591A1
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- 239000004065 semiconductor Substances 0.000 title description 65
- 239000000872 buffer Substances 0.000 claims abstract description 77
- 239000003990 capacitor Substances 0.000 claims abstract description 69
- 238000010586 diagram Methods 0.000 description 21
- 238000004364 calculation method Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/0405—Non-linear filters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
本発明は、日本国特許出願:特願2011−248276号(2011年11月14日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
第1の実施形態について、図面を用いてより詳細に説明する。
11 インターポーザ
12、30 ダイ
13 パッド
14 電源配線
15 接地配線
16、17 半田ボール
18、19 デカップリング用コンデンサ
20 電源
21、23 デカップリング用コンデンサの等価回路
22、24 プリント基板の等価回路
25、52 スルーホールの等価回路
26、51 インターポーザの等価回路
27 ダイの等価回路
28、32〜36、200 出力バッファ
31 内部回路
37 未使用バッファ
38、300 コンデンサ
40 半導体装置
41〜45 入力バッファ
50 Pチャンネル型MOSトランジスタのオン抵抗の等価回路
53、62 コンデンサの等価回路
60 バイパスコンデンサ等価回路
61 ダイ等価回路
63、70 RC回路の等価回路
100 デカップリング回路
N01、N02 Nチャンネル型MOSトランジスタ
P01、P02 Pチャンネル型MOSトランジスタ
R01、R02 トランジスタのオン抵抗
SW01、SW02 スイッチ
Claims (4)
- トランジスタを含む出力バッファと、
前記出力バッファの出力ノードに一端が接続され、他の一端が電源線に接続されているコンデンサと、
を備え、
前記出力バッファの出力ノードが出力する論理レベルは固定されていることを特徴とするデカップリング回路。 - 前記出力バッファは、第1導電型MOSトランジスタ及び第2導電型MOSトランジスタから構成される請求項1のデカップリング回路。
- 前記第1導電型MOSトランジスタはPチャンネル型MOSトランジスタであり、前記第2導電型MOSトランジスタはNチャンネル型MOSトランジスタであり、前記コンデンサが接地電圧に接続されている場合には、前記Pチャンネル型MOSトランジスタをオン状態とし、前記コンデンサが電源電圧に接続されている場合には、前記Nチャンネル型MOSトランジスタをオン状態とする請求項2のデカップリング回路。
- トランジスタを含む複数の出力バッファと、
前記複数の出力バッファのうち、外部に信号を伝達する動作に寄与しない未使用バッファの出力ノードに一端が接続され、他の一端が電源線に接続されているコンデンサと、
を備え、
前記未使用バッファの出力ノードが出力する論理レベルは固定されていることを特徴とする半導体集積回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013544305A JP5812103B2 (ja) | 2011-11-14 | 2012-11-14 | デカップリング回路及び半導体集積回路 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011248276 | 2011-11-14 | ||
JP2011248276 | 2011-11-14 | ||
PCT/JP2012/079545 WO2013073591A1 (ja) | 2011-11-14 | 2012-11-14 | デカップリング回路及び半導体集積回路 |
JP2013544305A JP5812103B2 (ja) | 2011-11-14 | 2012-11-14 | デカップリング回路及び半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2013073591A1 true JPWO2013073591A1 (ja) | 2015-04-02 |
JP5812103B2 JP5812103B2 (ja) | 2015-11-11 |
Family
ID=48429646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013544305A Expired - Fee Related JP5812103B2 (ja) | 2011-11-14 | 2012-11-14 | デカップリング回路及び半導体集積回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9166560B2 (ja) |
JP (1) | JP5812103B2 (ja) |
CN (1) | CN103959457B (ja) |
WO (1) | WO2013073591A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016092833A1 (ja) | 2014-12-10 | 2016-06-16 | 日本電気株式会社 | 電子回路、及び、電子回路の実装方法 |
US9438225B1 (en) * | 2015-06-11 | 2016-09-06 | Applied Micro Circuits Corporation | High efficiency half-cross-coupled decoupling capacitor |
US9525349B1 (en) | 2015-10-05 | 2016-12-20 | Via Alliance Semiconductor Co., Ltd. | Power supply decoupling circuit with decoupling capacitor |
US10581414B2 (en) * | 2015-10-14 | 2020-03-03 | Mediatek Inc. | Semiconductor integrated circuit device |
US11116072B2 (en) * | 2017-07-05 | 2021-09-07 | Intel Corporation | Discrete circuit having cross-talk noise cancellation circuitry and method thereof |
US11309246B2 (en) | 2020-02-05 | 2022-04-19 | Apple Inc. | High density 3D interconnect configuration |
Citations (5)
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JP2003086699A (ja) * | 2001-09-14 | 2003-03-20 | Nec Corp | 半導体回路、半導体集積回路装置、半導体装置のマクロを記憶した記憶装置及びマクロを記憶した記憶媒体 |
JP2006032823A (ja) * | 2004-07-21 | 2006-02-02 | Hitachi Ltd | 半導体装置 |
JP2006304346A (ja) * | 2006-06-15 | 2006-11-02 | Nec Electronics Corp | 半導体集積回路及びその設計・製造方法 |
JP2008520109A (ja) * | 2004-11-12 | 2008-06-12 | テキサス インスツルメンツ インコーポレイテッド | 切替可能i/oデカップリング・キャパシタンス機能を実現する局部esdパワーレールクランプ |
JP2011124615A (ja) * | 2009-12-08 | 2011-06-23 | Renesas Electronics Corp | 半導体集積回路、半導体装置及び電子機器 |
Family Cites Families (8)
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US5376843A (en) * | 1992-08-11 | 1994-12-27 | Integrated Device Technology, Inc. | TTL input buffer with on-chip reference bias regulator and decoupling capacitor |
US5828259A (en) * | 1996-11-18 | 1998-10-27 | International Business Machines Corporation | Method and apparatus for reducing disturbances on an integrated circuit |
JP3309898B2 (ja) * | 1997-06-17 | 2002-07-29 | 日本電気株式会社 | 電源回路 |
US6191628B1 (en) * | 1999-01-04 | 2001-02-20 | International Business Machines Corporation | Circuit for controlling the slew rate of a digital signal |
JP4420156B2 (ja) * | 2000-06-14 | 2010-02-24 | 日本電気株式会社 | 半導体装置 |
JP2006295027A (ja) | 2005-04-14 | 2006-10-26 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP5260193B2 (ja) | 2008-09-03 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | 半導体集積回路及びそのスイッチングノイズ平準化方法 |
JP2011009291A (ja) | 2009-06-23 | 2011-01-13 | Renesas Electronics Corp | 半導体集積回路の設計方法、半導体集積回路、電磁干渉の対策方法 |
-
2012
- 2012-11-14 CN CN201280055968.3A patent/CN103959457B/zh not_active Expired - Fee Related
- 2012-11-14 WO PCT/JP2012/079545 patent/WO2013073591A1/ja active Application Filing
- 2012-11-14 JP JP2013544305A patent/JP5812103B2/ja not_active Expired - Fee Related
- 2012-11-14 US US14/353,596 patent/US9166560B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003086699A (ja) * | 2001-09-14 | 2003-03-20 | Nec Corp | 半導体回路、半導体集積回路装置、半導体装置のマクロを記憶した記憶装置及びマクロを記憶した記憶媒体 |
JP2006032823A (ja) * | 2004-07-21 | 2006-02-02 | Hitachi Ltd | 半導体装置 |
JP2008520109A (ja) * | 2004-11-12 | 2008-06-12 | テキサス インスツルメンツ インコーポレイテッド | 切替可能i/oデカップリング・キャパシタンス機能を実現する局部esdパワーレールクランプ |
JP2006304346A (ja) * | 2006-06-15 | 2006-11-02 | Nec Electronics Corp | 半導体集積回路及びその設計・製造方法 |
JP2011124615A (ja) * | 2009-12-08 | 2011-06-23 | Renesas Electronics Corp | 半導体集積回路、半導体装置及び電子機器 |
Also Published As
Publication number | Publication date |
---|---|
CN103959457A (zh) | 2014-07-30 |
JP5812103B2 (ja) | 2015-11-11 |
US9166560B2 (en) | 2015-10-20 |
CN103959457B (zh) | 2016-10-12 |
WO2013073591A1 (ja) | 2013-05-23 |
US20140292399A1 (en) | 2014-10-02 |
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