JPWO2007086481A1 - 電子デバイスパッケージ、モジュール、および電子機器 - Google Patents
電子デバイスパッケージ、モジュール、および電子機器 Download PDFInfo
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- JPWO2007086481A1 JPWO2007086481A1 JP2007556003A JP2007556003A JPWO2007086481A1 JP WO2007086481 A1 JPWO2007086481 A1 JP WO2007086481A1 JP 2007556003 A JP2007556003 A JP 2007556003A JP 2007556003 A JP2007556003 A JP 2007556003A JP WO2007086481 A1 JPWO2007086481 A1 JP WO2007086481A1
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Abstract
Description
図2は第1の実施形態の半導体パッケージの縦断面図である。図3は、図2の半導体パッケージの上面図であるが、インターポーザ基板(可撓性基板)の図示は省略されている。
なお、図6(b)では、エッジを45°の角度で削っているが、図6(c)に示すようにさらに多角化すること、図6(d)に示すようにR面にすることで曲率をより一層小さくし、信頼性、高速動作性をさらに改善することが可能である。また、前記の挿入基板2に加工を施すほかに、図6(e)に示すように挿入基板2の端面に樹脂やはんだなどの突起を形成しても良い。
第1の実施形態では、枠状に形成された単一部材からなる挿入基板2が用いられていたが、本発明はこれに限らず、図7に示すような構成であってもよい。図7は第2の実施形態に係る半導体パッケージを示す上面図であるが、インターポーザ基板の図示は省略されている。なお、以下、第2〜第8の実施形態を例に挙げて本発明の構成例を幾つか説明するが、当然ながら、各実施形態で説明する構成を必要に応じて適宜組み合わせることも可能である。
第1の実施形態では、単層のインターポーザ基板5が用いられていたが、本発明はこれに限らず、図10に示すように多層のインターポーザ基板15が用いられていてもよい。図10の半導体パッケージ52は、第1の実施形態のパッケージにおいてインターポーザ基板5のみを変更したものであり、その他の構造部については第1の実施形態と同一である。
上記実施形態では、収容部に半導体デバイス1が1つだけ配置された構成であったが、本発明はこれに限らず、図11に示すように複数個の半導体デバイスが配置されていてもよい。図11の半導体デバイスの上面図(インターポーザ基板は不図示)は図11に示されており、また、図11は、図12のA−A切断線における断面図である。図11(a)、(b)に示す半導体パッケージ53A、53Bは、半導体デバイスの個数および配線形態を変更したものであり、その他の構造部については上記第3の実施形態と同一である。
上記実施形態では、基板2とグランドライン(または電源ライン)との接続が挿入基板の一方の面でのみなされたものであったが、本発明はこれに限らず図14に示すような構成であってもよい。
第1の実施形態(図2参照)では、挿入基板2に形成された開口部11内にデバイスが配置される構成となっていたが、本発明はこれに限らず、図15に示すように凹部(キャビティ)21内にデバイスが配置される構成であってもよい。以下、これについて図15、図16を参照して説明する。図15は、半導体パッケージの断面図であり、図16は図15のパッケージに用いられる挿入基板12および半導体デバイス1を下面側から見た斜視図である。なお、挿入基板12以外の他の構造部は、第1の実施形態のものと同一である。
第2の実施形態(例えば図5参照)では複数個の挿入基板が用いられていたが、この構成の場合、さらに下記のような構成とされていてもよい。
本発明に係る半導体パッケージ単体は、パッケージの上下面に電気的接続用の端子を形成可能であることから、幾つかの半導体パッケージを積層して使用するのに好適である。以下、これについて図20を参照して説明する。
実施例1として、第2の実施形態型(図7(a)参照)の半導体パッケージ51Aを作製した。
実施例2として、第4の実施形態型(図11(a)参照)の電子デバイスパッケージ53Aを作製した。
そこで、本実施例を用いて反射低減の効果を検証するため、それぞれの構造における配線のSパラメータ測定を行った。その結果、10GHzにおいて信号の強度損失がエッジ加工を施していないものに対してC面(90μm)の場合で約1dB、R面(半径100μm)の場合で約1.2dB低減され、形状としてはR面が最も信号の損失が小さいと言える。
実施例3として、第5の実施形態型(図14(b)参照)の半導体パッケージ54Bを作製した。
実施例4として、第7の実施形態型(図18参照)の半導体パッケージ56を作製した。
実施例5として、第8の実施形態型(図20(c)参照)の半導体パッケージ57Cを作製した。つまり、第2の実施形態型の半導体パッケージ52(図10参照;多層のインターポーザ基板を使用した構成)を作製すると共に、そのパッケージ上に従来の半導体パッケージ65を搭載した。
2、12、22 挿入基板
5、15 インターポーザ基板
6 熱可塑性樹脂
7、8 配線パターン
9 電極パッド
10 はんだボール
11、11A 開口部
13 注入孔
16 絶縁層
17a、17b 基板端部
18a〜18d 隙間
19、19’ デカップリングコンデンサ
21、21’ 凹部
23 段付き部
34、35 導体バンプ
40 エッジ
41 突起
50〜58 半導体パッケージ(電子デバイスパッケージ)
Claims (22)
- 回路面に外部電極が形成された電子デバイスと、前記電子デバイスが配置される収容部を形成する少なくとも1つの挿入基板と、前記電子デバイスと電気的に接続される配線パターンを備えると共に、少なくとも一部が前記挿入基板および/または前記電子デバイスに沿って折り曲げられた可撓性基板とを有する電子デバイスパッケージにおいて、前記挿入基板の少なくとも1つが導電性材料からなり、前記配線パターンのうちのグランドラインまたは電源ラインに電気的に接続されていることを特徴とする電子デバイスパッケージ。
- 前記挿入基板を少なくとも2つ有し、前記各挿入基板は、前記回路面と平行な面上に平面的に配置されている、請求項1に記載の電子デバイスパッケージ。
- 前記挿入基板を少なくとも2つ有し、前記各挿入基板は、絶縁層を介して前記挿入基板の厚み方向に積層されている、請求項1に記載の電子デバイスパッケージ。
- 前記挿入基板がその厚み方向に積層された積層体が、前記回路面と平行な面上に平面的に配置されている、請求項1に記載の電子デバイスパッケージ。
- 前記グランドラインに接続された前記挿入基板と、前記電源ラインに接続された前記挿入基板とを有する、請求項2から4のいずれか1項に記載の電子デバイスパッケージ。
- グランドラインに接続された前記挿入基板と、電源ラインに接続された前記挿入基板との間に、デカップリングコンデンサが配置されている、請求項5に記載の電子デバイスパッケージ。
- 前記挿入基板の端部同士の間に形成される隙間が、平面的に見て、同一直線上に揃わないように構成されている、請求項2、5、6に記載の電子デバイスパッケージ。
- 前記収容部が貫通穴状に構成されている、請求項1から7のいずれか1項に記載の電子デバイスパッケージ。
- 前記挿入基板の厚みまたは前記挿入基板同士を積層させた積層体の厚みと、前記電子デバイスの厚みとが同一である、請求項8に記載の電子デバイスパッケージ。
- 前記収容部が凹部状に構成されている、請求項1から7のいずれか1項に記載の電子デバイスパッケージ。
- 前記挿入基板と前記配線パターンとの電気的接続が、前記挿入基板の両面でなされている、請求項1から10のいずれか1項に記載の電子デバイスパッケージ。
- 前記挿入基板と前記配線パターンとの電気的接続が、導体バンプを介して行われている、請求項1から11のいずれか1項に記載の電子デバイスパッケージ。
- 前記収容部内に、前記電子デバイスが複数個配置されている、請求項1から12のいずれか1項に記載の電子デバイスパッケージ。
- 前記可撓性基板は、前記配線パターンが2層以上形成された多層型のものである、請求項1から13のいずれか1項に記載の電子デバイスパッケージ。
- 前記可撓性基板は、前記挿入基板および/または前記電子デバイスに接する内周面の少なくとも一部が、熱可塑性樹脂で形成されている、請求項1から14のいずれか1項に記載の電子デバイスパッケージ。
- 前記電源ラインまたは前記グランドラインのいずれにも接続されない前記挿入基板を少なくとも1つ有する、請求項1から15のいずれか1項に記載の電子デバイスパッケージ。
- 前記挿入基板の、前記配線パターン折り曲げ部に相当する少なくとも一部が、角多形もしくは円弧になっていることを特徴とする請求項1から16のいずれか1項に記載の電子デバイスパッケージ。
- 前記挿入基板の、前記配線パターンの折り曲げに用いる側面の少なくとも一部に、曲面の突起を設け、屈曲部をなくす、もしくは屈曲の度合いを低減していることを特徴とする、請求項1から16のいずれか1項に記載の電子デバイスパッケージ。
- 請求項1から18のいずれか1項に記載の同種の前記電子デバイスパッケージ同士、または、請求項1から18に記載の電子デバイスパッケージから選択された異なる種類の前記電子デバイスパッケージ同士が複数個積層された電子デバイスパッケージ。
- 電子デバイスが複数個積層された電子デバイスパッケージであって、請求項1から18のいずれか1項に記載の前記電子デバイスパッケージを少なくとも1つ含んだ電子デバイスパッケージ。
- 請求項1から20のいずれか1項に記載の電子デバイスパッケージが実装基板上に配置されたモジュール。
- 請求項21に記載のモジュールを搭載した電子機器。
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US20100246144A1 (en) | 2010-09-30 |
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