JPWO2007040285A1 - マルチチャネル駆動回路 - Google Patents
マルチチャネル駆動回路 Download PDFInfo
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- JPWO2007040285A1 JPWO2007040285A1 JP2007511114A JP2007511114A JPWO2007040285A1 JP WO2007040285 A1 JPWO2007040285 A1 JP WO2007040285A1 JP 2007511114 A JP2007511114 A JP 2007511114A JP 2007511114 A JP2007511114 A JP 2007511114A JP WO2007040285 A1 JPWO2007040285 A1 JP WO2007040285A1
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
チャネル間でバラツキを生ずる場合にも、負荷アレイを構成する各チャネル
の負荷を全チャネルに亘り均一な条件で駆動可能としたマルチチャネル駆動
回路を提供すること。
電流源アレイ(11)を構成する各チャネルの電流源のそれぞれと、入力
スイッチアレイ(13)を構成する各チャネルの入力スイッチのそれぞれと
を結ぶ各チャネルの電流路のそれぞれを互いに導通させるためのチャネル間
共通接続線(5)と、複数チャネルのうちで、入力スイッチがオフ状態にあ
るチャネルに関しては、そのチャネルの電流源の出力電流がチャネル間共通
接続線に流れることを阻止する電流阻止手段(12)と、を含んで構成され
る。
Description
Ia={(I11k)+(I11k+1)+
(I11k+2)+(I11k+3)}÷4・・・(2)
I13k=I13k+1=I13k+2=I13k+3=Ia1
Ia1={(I11k)+(I11k+1)+(I11k+2)
+(I11k+3)}÷4
となる。また、時刻t2〜t3の期間では、オン状態にある2つのチャネルの負荷電流I13k+1,I13k+3の値は、
I13k+1=I13k+3=Ia2
Ia2={(I11k+1)+(I11k+3)}÷2
となる。また、時刻t3〜t4の期間では、オン状態にある1つのチャネルの負荷電流I13k+1の値は、
I13k+1=I11k+1となる。
2 負側電源ライン
3 正側バイアス電源ライン
4 負側バイアス電源ライン
5 (正側)チャネル間共通接続線
5a 正側チャネル間共通接続線
5k〜5k+3,5ak〜5ak+3 (正側)チャネル間共通接続線の接続点
5R,5G,5B 正側のRGB別チャネル間共通接続線
6 (負側)チャネル間共通接続線
6a 負側チャネル間共通接続線
6k〜6k+3,6ak〜6ak+3 (負側)チャネル間共通接続線の接続点
6R,6G,6B 負側のRGB別チャネル間共通接続線
7 放流ライン用のチャネル間共通接続線
8 プリチャージ電源ライン
10k〜10k+3 要素回路
11 (正側)電流源アレイ
11k〜11k+3 (正側)電流源トランジスタ
12k〜12k+3 (正側)電流阻止用のスイッチトランジスタ
13,13a (正側)入力用のスイッチアレイ
13k〜13k+3 (正側)入力用のスイッチトランジスタ
14k〜14k+3 (正側)スイッチ制御信号
15k〜15k+3 (正側)バイアス用のスイッチトランジスタ
16k〜16k+3 (正側)カットオフ用のスイッチトランジスタ
17 正側変調型電流源アレイ
17k〜17k+3 正側変調型電流源
18k〜18k+3 電流放流用のスイッチトランジスタ
19k〜19k+3 ダミー負荷用の電流源トランジスタ
21,21a (負側)電流源アレイ
21k〜21k+3 (負側)電流源トランジスタ
22k〜22k+3 (負側)電流阻止用のスイッチトランジスタ
23 (負側)入力用のスイッチアレイ
23k〜23k+3 (負側)入力用のスイッチトランジスタ
24k〜24k+3 (負側)スイッチ制御信号
25k〜25k+3 (負側)バイアス用のスイッチトランジスタ
26k〜26k+3 (負側)カットオフ用のスイッチトランジスタ
27 負側変調型電流源アレイ
27k〜27k+3 負側変調型電流源
30 バイアス電源回路
37k〜37k+3 インバータ
40 負荷アレイ
40k〜40k+3 負荷
47k〜47k+3 インバータ
50 接続用導体
50n 負側の接続導体
50p 正側の接続導体
60 走査ドライバ
61,62,63 重み付け値別のチャネル間共通接続線
70k,70k+1 プリチャージ用アナログスイッチ
81k 正側の補助トランジスタ
82k,83k 接続点
84k 負側の補助トランジスタ
100 マルチチャネル駆動回路
101,101k−1,101k,101k+1 ICチップ
102 パッケージ
170−1k〜3k 正側の補助トランジスタ
171k〜171k+1,172k〜172k+1,173k〜173k+1 重み付け値別電流源トランジスタ
174k〜174k+1,175k〜175k+1,176k〜176k+1 重み付け値別電流阻止用のスイッチトランジスタ
177k〜177k+1,178k〜178k+1,179k〜179k+1 重み付け値別のNANDゲート
270−1k〜3k 負側の補助トランジスタ
271k〜271k+1,272k〜272k+1,273k〜273k+1 重み付け値別電流源トランジスタ
274k〜274k+1,275k〜275k+1,276k〜276k+1 重み付け値別電流阻止用のスイッチトランジスタ
277k〜177k+1,278k〜278k+1,279k〜279k+1 重み付け値別のNANDゲート
511,512,513 正側のRGB別接続用導体
521,522,523 負側のRGB別接続用導体
BP1〜BP3 正側重み付け値選択信号
BN1〜BN3 負側重み付け値選択信号
I11k〜I11k+3 (正側)電流源トランジスタの設定電流
I13k〜I13k+3 負荷電流
OUTk〜OUTk+3 出力端子
PDL 左側用接続パッド
PDL21,PDL22,PDL23 負側の左側用接続パッド
PDR 右側用接続パッド
PDR11,PDR12,PDR13 正側の右側用接続パッド
Tp 正側の外部接続端子
Tn 負側の外部接続端子
Vk〜Vk+3 出力端子の電位
VBH 正側バイアス電源
VBL 負側バイアス電源
VDD 正側電源
VSS 負側電源
Vx プリチャージ用電源
I13k=I13k+1=I13k+2=I13k+3=Ia・・・(1)
Ia={(I11k)+(I11k+1)+
(I11k+2)+(I11k+3)}÷4・・・(2)
すなわち、4個の電流源トランジスタ11k〜11k+3の設定電流値I11k〜I11k+3にチャネル間でバラツキがあったとしても、各チャネルの負荷電流値13k〜13k+3は、平均電流値Iaに相当する均一な値に維持される。
I13k=I13k+1=I13k+2=I13k+3=Ia1
Ia1={(I11k)+(I11k+1)+(I11k+2)
+(I11k+3)}÷4
となる。また、時刻t2〜t3の期間では、オン状態にある2つのチャネルの負荷電流I13k+1,I13k+3の値は、
I13k+1=I13k+3=Ia2
Ia2={(I11k+1)+(I11k+3)}÷2
となる。また、時刻t3〜t4の期間では、オン状態にある1つのチャネルの負荷電流I13k+1の値は、
I13k+1=I11k+1となる。
2 負側電源ライン
3 正側バイアス電源ライン
4 負側バイアス電源ライン
5 (正側)チャネル間共通接続線
5a 正側チャネル間共通接続線
5k〜5k+3,5ak〜5ak+3 (正側)チャネル間共通接続線の接続点
5R,5G,5B 正側のRGB別チャネル間共通接続線
6 (負側)チャネル間共通接続線
6a 負側チャネル間共通接続線
6k〜6k+3,6ak〜6ak+3 (負側)チャネル間共通接続線の接続点
6R,6G,6B 負側のRGB別チャネル間共通接続線
7 放流ライン用のチャネル間共通接続線
8 プリチャージ電源ライン
10k〜10k+3 要素回路
11 (正側)電流源アレイ
11k〜11k+3 (正側)電流源トランジスタ
12k〜12k+3 (正側)電流阻止用のスイッチトランジスタ
13,13a (正側)入力用のスイッチアレイ
13k〜13k+3 (正側)入力用のスイッチトランジスタ
14k〜14k+3 (正側)スイッチ制御信号
15k〜15k+3 (正側)バイアス用のスイッチトランジスタ
16k〜16k+3 (正側)カットオフ用のスイッチトランジスタ
17 正側変調型電流源アレイ
17k〜17k+3 正側変調型電流源
18k〜18k+3 電流放流用のスイッチトランジスタ
19k〜19k+3 ダミー負荷用の電流源トランジスタ
21,21a (負側)電流源アレイ
21k〜21k+3 (負側)電流源トランジスタ
22k〜22k+3 (負側)電流阻止用のスイッチトランジスタ
23 (負側)入力用のスイッチアレイ
23k〜23k+3 (負側)入力用のスイッチトランジスタ
24k〜24k+3 (負側)スイッチ制御信号
25k〜25k+3 (負側)バイアス用のスイッチトランジスタ
26k〜26k+3 (負側)カットオフ用のスイッチトランジスタ
27 負側変調型電流源アレイ
27k〜27k+3 負側変調型電流源
30 バイアス電源回路
37k〜37k+3 インバータ
40 負荷アレイ
40k〜40k+3 負荷
47k〜47k+3 インバータ
50 接続用導体
50n 負側の接続導体
50p 正側の接続導体
60 走査ドライバ
61,62,63 重み付け値別のチャネル間共通接続線
70k,70k+1 プリチャージ用アナログスイッチ
81k 正側の補助トランジスタ
82k,83k 接続点
84k 負側の補助トランジスタ
100 マルチチャネル駆動回路
101,101k−1,101k,101k+1 ICチップ
102 パッケージ
170−1k〜3k 正側の補助トランジスタ
171k〜171k+1,172k〜172k+1,173k〜173k+1 重み付け値別電流源トランジスタ
174k〜174k+1,175k〜175k+1,176k〜176k+1 重み付け値別電流阻止用のスイッチトランジスタ
177k〜177k+1,178k〜178k+1,179k〜179k+1 重み付け値別のNANDゲート
270−1k〜3k 負側の補助トランジスタ
271k〜271k+1,272k〜272k+1,273k〜273k+1 重み付け値別電流源トランジスタ
274k〜274k+1,275k〜275k+1,276k〜276k+1 重み付け値別電流阻止用のスイッチトランジスタ
277k〜177k+1,278k〜278k+1,279k〜279k+1 重み付け値別のNANDゲート
511,512,513 正側のRGB別接続用導体
521,522,523 負側のRGB別接続用導体
BP1〜BP3 正側重み付け値選択信号
BN1〜BN3 負側重み付け値選択信号
I11k〜I11k+3 (正側)電流源トランジスタの設定電流
I13k〜I13k+3 負荷電流
OUTk〜OUTk+3 出力端子
PDL 左側用接続パッド
PDL21,PDL22,PDL23 負側の左側用接続パッド
PDR 右側用接続パッド
PDR11,PDR12,PDR13 正側の右側用接続パッド
Tp 正側の外部接続端子
Tn 負側の外部接続端子
Vk〜Vk+3 出力端子の電位
VBH 正側バイアス電源
VBL 負側バイアス電源
VDD 正側電源
VSS 負側電源
Vx プリチャージ用電源
Claims (9)
- 複数チャネルのそれぞれに対応する複数の電流源を含む電流源アレイと、
複数チャネルのそれぞれに対応する複数の入力スイッチを含む入力スイッチアレイと、を含み、
電流源アレイを構成する各チャネルの電流源のそれぞれにより、入力スイッチアレイを構成する各チャネルの入力スイッチのそれぞれを介して、負荷アレイを構成する各チャネルの負荷のそれぞれに対して通電を行うマルチチャネル負荷駆動回路であって、
電流源アレイを構成する各チャネルの電流源のそれぞれと、入力スイッチアレイを構成する各チャネルの入力スイッチのそれぞれとを結ぶ各チャネルの電流路のそれぞれを互いに導通させるためのチャネル間共通接続線と、
複数チャネルのうちで、入力スイッチがオフ状態にあるチャネルに関しては、そのチャネルの電流源の出力電流がチャネル間共通接続線に流れることを阻止する電流阻止手段と、
を具備する、ことを特徴とするマルチチャネル駆動回路。 - 電流源アレイが、複数チャネルのそれぞれに対応する複数の正側電流源を含む正側電流源アレイと、複数チャネルのそれぞれに対応する複数の負側電流源を含む負側電流源アレイと、を含み、
入力スイッチアレイが、複数チャネルのそれぞれに対応する複数の正側入力スイッチを含む正側入力スイッチアレイと、複数チャネルのそれぞれに対応する複数の負側入力スイッチを含む負側入力スイッチアレイと、を含み、
正側電流源アレイを構成する各チャネルの正側電流源のそれぞれにより、正側入力スイッチアレイを構成する各チャネルの正側入力スイッチのそれぞれを介して、負荷アレイを構成する各チャネルの負荷のそれぞれに対して正側通電を行ない、かつ
負側電流源アレイを構成する各チャネルの負側電流源のそれぞれにより、負側入力スイッチアレイを構成する各チャネルの負側入力スイッチのそれぞれを介して、負荷アレイを構成する各チャネルの負荷のそれぞれに対して負側通電を行なうように仕組まれており、さらに
チャネル間共通接続線が、
正側電流源アレイを構成する各チャネルの正側電流源のそれぞれと、正側入力スイッチアレイを構成する各チャネルの正側入力スイッチのそれぞれとを結ぶ各チャネルの電流路のそれぞれを互いに導通させるための正側チャネル間共通接続線と、負側電流源アレイを構成する各チャネルの負側電流源のそれぞれと、負側入力スイッチアレイを構成する各チャネルの負側入力スイッチのそれぞれとを結ぶ各チャネルの電流路のそれぞれを互いに導通させるための負側チャネル間共通接続線と、を含み、
電流阻止手段が、
複数チャネルのうちで、正側入力スイッチがオフ状態にあるチャネルに関しては、そのチャネルの正側電流源の出力電流がチャネル間共通接続線に流れることを阻止する正側電流阻止手段と、複数チャネルのうちで、負側入力スイッチがオフ状態にあるチャネルに関しては、そのチャネルの負側電流源の出力電流がチャネル間共通接続線に流れることを阻止する負側電流阻止手段と、を含む、
ことを特徴とする請求項1に記載のマルチチャネル駆動回路。 - 負荷アレイを構成する各チャネルの負荷が、RGBのそれぞれに対応する3個の容量性画素で構成されており、
電流源アレイを構成する各チャネルの電流源が、R画素ガンマ補正用の電流源とG画素ガンマ補正用の電流源とB画素ガンマ補正用の電流源とにより構成されており、さらに
チャネル間共通接続線が、R画素ガンマ補正用の電流源同士を結ぶ第1のチャネル間共通接続線と、G画素ガンマ補正用の電流源同士を結ぶ第2のチャネル間共通接続線と、B画素ガンマ補正用の電流源同士を結ぶ第3のチャネル間共通接続線とを含んでいる、
ことを特徴とする請求項1に記載のマルチチャネル駆動回路。 - 電流源アレイを構成する各チャネルの電流源が、重み付け値の異なる複数の単位電流源と、それら単位電流源の出力経路のそれぞれに介在された単位スイッチとで構成され、それらの単位スイッチを介して選択された単位電流源の出力電流が加算されて、目的とする設定電流値が生成され、かつ各単位スイッチがプログラムされた手順で時間と共にオンオフすることで、設定電流値が一定のプロファイルを描いて時間と共に変化する変調型電流源が実現され、さらに
チャネル間共通接続線が、重み付け値が同一な単位電流源同士を結ぶ複数本の重み付け値別のチャネル間共通接続線により構成される、
ことを特徴とする請求項1に記載のマルチチャネル駆動回路。 - 電流阻止手段が、入力スイッチがオフ状態にあるとき、電流源とチャネル間共通接続線とを結ぶ電流路における通電を遮断するように仕組まれている、ことを特徴とする請求項1〜4のいずれかに記載のマルチチャネル駆動回路。
- 電流阻止手段が、入力スイッチがオフ状態にあるとき、電流源を不能化するように仕組まれている、ことを特徴とする請求項1〜4のいずれかに記載のマルチチャネル駆動回路。
- 電流阻止手段が、入力スイッチがオフ状態にあるとき、電流源を流れる電流を入力スイッチをバイパスさせて放流するように仕組まれている、ことを特徴とする請求項1〜3のいずれかに記載のマルチチャネル駆動回路。
- 複数チャネルのそれぞれに対応する複数の電流源を含む電流源アレイと、
複数チャネルのそれぞれに対応する複数の負荷接続用の外部端子を含む外部端子アレイと、
電流源アレイと外部端子アレイとの間に介在され、かつ複数チャネルのそれぞれに対応する複数の入力スイッチを含む入力スイッチアレイと、
電流源アレイを構成する各チャネルの電流源のそれぞれと、入力スイッチアレイを構成する各チャネルの入力スイッチのそれぞれとを結ぶ各チャネルの電流路のそれぞれを互いに導通させるためのチャネル間共通接続線と、
複数チャネルのうちで、入力スイッチがオフ状態にあるチャネルに関しては、そのチャネルの電流源の出力電流がチャネル間共通接続線に流れることを阻止する電流阻止手段と、を含み、かつ
チャネル間共通接続線は十分に幅広とされ、かつその材質としてはアルミ等の低抵抗金属材料が使用されている、ことを特徴とするマルチチャネル駆動回路として機能する半導体集積装置。 - マルチチャネル負荷駆動回路を構成する半導体チップは所定のパッケージに収容されており、かつそのパッケージにはチャネル間共通接続線を外部に導出するための外部端子が設けられている、ことを特徴とする請求項8に記載の半導体集積装置。
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JPPCT/JP2006/310753 | 2006-05-30 | ||
PCT/JP2006/310753 WO2007094088A1 (ja) | 2006-02-15 | 2006-05-30 | マルチチャネル駆動回路 |
PCT/JP2006/323084 WO2007040285A1 (ja) | 2006-02-15 | 2006-11-20 | マルチチャネル駆動回路 |
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CN101630950B (zh) * | 2008-07-16 | 2011-09-28 | 联咏科技股份有限公司 | 多通道驱动电路及其驱动方法 |
US8854294B2 (en) * | 2009-03-06 | 2014-10-07 | Apple Inc. | Circuitry for independent gamma adjustment points |
CN101840689B (zh) * | 2010-05-14 | 2013-06-05 | 中兴通讯股份有限公司 | 校正LCD屏gamma值的方法和装置 |
CN102376288B (zh) * | 2010-08-04 | 2015-09-30 | 晨星软件研发(深圳)有限公司 | 多模态的传送输出电路 |
US9270258B2 (en) | 2011-11-16 | 2016-02-23 | National University Corporation Shizuoka University | Lamp signal generation circuit and CMOS image sensor |
US8610612B2 (en) * | 2012-02-24 | 2013-12-17 | Integrated Device Technology, Inc. | Tree structured supply and bias distribution layout |
CN104361858B (zh) * | 2014-11-12 | 2016-10-12 | 京东方科技集团股份有限公司 | 电压驱动像素电路、显示面板及其驱动方法 |
US10032775B2 (en) * | 2015-05-29 | 2018-07-24 | Rohde & Schwarz Gmbh & Co. Kg | Switching device for switching radio frequency signals |
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WO2007094088A1 (ja) | 2007-08-23 |
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EP1986178A1 (en) | 2008-10-29 |
JP3848358B1 (ja) | 2006-11-22 |
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