JPS6473729A - Formation of thin film - Google Patents

Formation of thin film

Info

Publication number
JPS6473729A
JPS6473729A JP23131387A JP23131387A JPS6473729A JP S6473729 A JPS6473729 A JP S6473729A JP 23131387 A JP23131387 A JP 23131387A JP 23131387 A JP23131387 A JP 23131387A JP S6473729 A JPS6473729 A JP S6473729A
Authority
JP
Japan
Prior art keywords
film
glass
substrate
apertures
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23131387A
Other languages
Japanese (ja)
Inventor
Kosaku Yano
Tetsuya Ueda
Hiroshi Nishimura
Shoichi Tanimura
Kazuyuki Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23131387A priority Critical patent/JPS6473729A/en
Publication of JPS6473729A publication Critical patent/JPS6473729A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To remove OH or C in an interlayer insulating film at low temperature and to uniformize connecting holes to be provided in the film afterwards by a method wherein, when a glass is coated on a substrate, is heated and cured and is used as the interlayer insulating film between metallic wirings, the glass is exposed to an active oxygen containing atmosphere generated by light irradiation during heating or after heating. CONSTITUTION:Al wiring patterns 23 are provided on a substrate 11, these exposed external surfaces are covered with an SiO2 film 13 formed by a plasma CVD method and a liquid glass is spin coated on the whole surface and is subjected to heating treatment. After that, the substrate 11 is held in an oxygen- containing atmosphere and an ArF excimer laser beam is irradiated to produce an insulating film 14 on the glass. Then, the whole surface is covered with an SiO2 film 15, a dry etching is performed using a resist pattern 16 having apertures to correspond to the patterns 12 as a mask to bore apertures to penetrate the films 13 and 14 and a second wiring pattern 17 consisting of Al is adhered on the exposed patterns 12. According to such a way, the amount of OH or C in the film 14 can be decreased and the precision of the apertures to be provided here is improved.
JP23131387A 1987-09-16 1987-09-16 Formation of thin film Pending JPS6473729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23131387A JPS6473729A (en) 1987-09-16 1987-09-16 Formation of thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23131387A JPS6473729A (en) 1987-09-16 1987-09-16 Formation of thin film

Publications (1)

Publication Number Publication Date
JPS6473729A true JPS6473729A (en) 1989-03-20

Family

ID=16921675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23131387A Pending JPS6473729A (en) 1987-09-16 1987-09-16 Formation of thin film

Country Status (1)

Country Link
JP (1) JPS6473729A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365424B1 (en) * 1998-10-28 2003-03-31 주식회사 하이닉스반도체 Method of forming interconnection line for semiconductor device
JP2008511135A (en) * 2004-08-20 2008-04-10 インターナショナル・ビジネス・マシーンズ・コーポレーション DUV laser annealing and stabilization of SiCOH films

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365424B1 (en) * 1998-10-28 2003-03-31 주식회사 하이닉스반도체 Method of forming interconnection line for semiconductor device
JP2008511135A (en) * 2004-08-20 2008-04-10 インターナショナル・ビジネス・マシーンズ・コーポレーション DUV laser annealing and stabilization of SiCOH films

Similar Documents

Publication Publication Date Title
ATE185430T1 (en) METHOD FOR PRODUCING PATTERNS
DE69330921D1 (en) Manufacturing process of thin film
JPS6411717B2 (en)
JPS6473729A (en) Formation of thin film
JPS5727029A (en) Formation of mo pattern
JPS5730337A (en) Formation of surface protecting film for semiconductor
JPS56140345A (en) Formation of pattern
JPS55160431A (en) Method for etching treatment
JPS5448485A (en) Photo etching method
JPS56125856A (en) Manufacture of semiconductor device
JPS5680130A (en) Manufacture of semiconductor device
JPS566434A (en) Manufacture of semiconductor device
JPS56107241A (en) Dry etching method
JPS56115537A (en) Forming method of infinitesimal pattern
JPS577934A (en) Method for forming fine pattern
JPS6447024A (en) Formation of pattern
JPS5587436A (en) Method of producing semiconductor device
JPS6479743A (en) Pattern forming method by dry developing
JPS6457618A (en) Pattern forming method
JPS5710930A (en) Dry development method
JPS5745234A (en) Method for formation of microscopic pattern
JPS57173943A (en) Manufacture of photo mask
JPS6489435A (en) Dissolution removing method of resist
JPS56115534A (en) Formation of pattern
JPS5626440A (en) Method for fine pattern formation