JPS5626440A - Method for fine pattern formation - Google Patents

Method for fine pattern formation

Info

Publication number
JPS5626440A
JPS5626440A JP10134879A JP10134879A JPS5626440A JP S5626440 A JPS5626440 A JP S5626440A JP 10134879 A JP10134879 A JP 10134879A JP 10134879 A JP10134879 A JP 10134879A JP S5626440 A JPS5626440 A JP S5626440A
Authority
JP
Japan
Prior art keywords
resist
negative
wafer
resists
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10134879A
Other languages
Japanese (ja)
Inventor
Hiroo Mizogami
Sadao Suganuma
Sojiro Fukuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10134879A priority Critical patent/JPS5626440A/en
Publication of JPS5626440A publication Critical patent/JPS5626440A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a fine pattern by applying a positive resist mask to the negative film on a semiconductor substrate and by opening the negative resist film wherein a conductor thin film is formed on the exposed substrate and an unnecessary conductor is lifted off with the resist film. CONSTITUTION:A negative resist 22 is applied to a wafer 21 completed element formation and the resist and wafer are polymerized by exposure or by heat treatment and positive resist masks 23 are applied on the negative resist 22. The resist 22 is ashed by O2 plasma and the flaws of the positive resists 23 generate if the wafer 21 is exposed. Al24 is evaporated and after immersing in a resist exfoliation liquid, the resists, 22, 23 and the Al24 located on the resists 22, 23 will be removed. And burr will not occur and a high precision Al pattern will be formed.
JP10134879A 1979-08-10 1979-08-10 Method for fine pattern formation Pending JPS5626440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10134879A JPS5626440A (en) 1979-08-10 1979-08-10 Method for fine pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10134879A JPS5626440A (en) 1979-08-10 1979-08-10 Method for fine pattern formation

Publications (1)

Publication Number Publication Date
JPS5626440A true JPS5626440A (en) 1981-03-14

Family

ID=14298322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10134879A Pending JPS5626440A (en) 1979-08-10 1979-08-10 Method for fine pattern formation

Country Status (1)

Country Link
JP (1) JPS5626440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459918A (en) * 1987-08-31 1989-03-07 Nec Corp Lift-off flattening process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5270780A (en) * 1975-12-10 1977-06-13 Toshiba Corp Manufacture of semiconductor device
JPS5348947A (en) * 1976-10-18 1978-05-02 Oki Electric Ind Co Ltd Photoethcing method for oxidized film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5270780A (en) * 1975-12-10 1977-06-13 Toshiba Corp Manufacture of semiconductor device
JPS5348947A (en) * 1976-10-18 1978-05-02 Oki Electric Ind Co Ltd Photoethcing method for oxidized film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459918A (en) * 1987-08-31 1989-03-07 Nec Corp Lift-off flattening process

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