JPS6457733A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the concentration of stress from a passivation film and the generation of a cavity in the passivation film by tapering an upper edge in the cross section of a wiring for a semiconductor device. CONSTITUTION:An Al alloy layer 104 is deposited onto an inter-layer insulating film 103, to which a contact hole 102 is formed, on a semiconductor substrate 101 through a sputtering method, and a resist layer 105 is shaped and patterned. Approximately one third or half of the film thickness of an Al alloy is etched in an isotropic manner through wet etching first, and the layer 105 is etched in an anisotropic manner through dry etching using an etching gas. A resist is peeled, and an SiN film 106 is deposited as a passivation film. An upper section is tapered, and corners are increased, thus dispersing stress, then reducing the growth of voids and notches.