JPS5553442A - Formation of electrode and wiring layer of semiconductor device - Google Patents
Formation of electrode and wiring layer of semiconductor deviceInfo
- Publication number
- JPS5553442A JPS5553442A JP12704478A JP12704478A JPS5553442A JP S5553442 A JPS5553442 A JP S5553442A JP 12704478 A JP12704478 A JP 12704478A JP 12704478 A JP12704478 A JP 12704478A JP S5553442 A JPS5553442 A JP S5553442A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pattern
- wiring layer
- electrode wiring
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To obtain an Al electrode wiring layer with a fine pattern by getting a thin W protective layer adhered to the surface of the Al electrode wiring layer; covering regions other than those specified with photosensitive resin; and removing only the W layer and the Al layer under the resin after plasma-etching.
CONSTITUTION: Making a SiO2 layer 2 grow on Si substrate 1 where an active region 4 has been formed and boring a hole through the region 4, an Al layer 3 is made to stick to the surface including the opening, using the sputtering method. Next the Al layer is covered with a thin protective W layer 5 through the sputtering method, than a pattern 6 composed of photosensitive resin is formed on the layer excluding the opening. Thenceforward, the wafer is treated in a gas plasme etching apparatus so as to remove the layers 5 and 3 under the pattern 6, then the layer 5 out of the remaining layers 5 and 3. The remaining layer 3 is made into an Al electrode wiring layer 3. It is due to reducing substances such as CO produced during decomposition that only the layers under the pattern are removed. The exposed layer 5 is not etched, and the reason for this is that there is WO3 which has an extremely high melting point.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12704478A JPS594857B2 (en) | 1978-10-16 | 1978-10-16 | Method for forming electrodes and wiring layers of semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12704478A JPS594857B2 (en) | 1978-10-16 | 1978-10-16 | Method for forming electrodes and wiring layers of semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5553442A true JPS5553442A (en) | 1980-04-18 |
JPS594857B2 JPS594857B2 (en) | 1984-02-01 |
Family
ID=14950222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12704478A Expired JPS594857B2 (en) | 1978-10-16 | 1978-10-16 | Method for forming electrodes and wiring layers of semiconductor devices |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS594857B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH063657U (en) * | 1992-06-22 | 1994-01-18 | ニッテン株式会社 | Seal |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63177381U (en) * | 1987-05-08 | 1988-11-17 |
-
1978
- 1978-10-16 JP JP12704478A patent/JPS594857B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH063657U (en) * | 1992-06-22 | 1994-01-18 | ニッテン株式会社 | Seal |
Also Published As
Publication number | Publication date |
---|---|
JPS594857B2 (en) | 1984-02-01 |
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