JPS6449261A - Manufacture of bipolar transistor - Google Patents

Manufacture of bipolar transistor

Info

Publication number
JPS6449261A
JPS6449261A JP20618187A JP20618187A JPS6449261A JP S6449261 A JPS6449261 A JP S6449261A JP 20618187 A JP20618187 A JP 20618187A JP 20618187 A JP20618187 A JP 20618187A JP S6449261 A JPS6449261 A JP S6449261A
Authority
JP
Japan
Prior art keywords
region
groove
device isolation
impurity
filled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20618187A
Other languages
Japanese (ja)
Other versions
JP2615652B2 (en
Inventor
Hiroki Hozumi
Takayuki Gomi
Minoru Nakamura
Akio Kashiwanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62206181A priority Critical patent/JP2615652B2/en
Publication of JPS6449261A publication Critical patent/JPS6449261A/en
Application granted granted Critical
Publication of JP2615652B2 publication Critical patent/JP2615652B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To avoid the thermal distortion and the re-distribution of an impurity by a method wherein, after a collector extraction region has been formed, a device isolation groove is formed and the groove is filled with a low- temperature vapor-phase growth operation. CONSTITUTION:An n<+> type buried region 2, an n<-> type collector layer 3, a field oxide film 4 and an n<+> collector extraction region 5 are formed on a p-type substrate 1. Then, a device isolation groove 6 is formed; a channel stop region 13 is formed on its bottom part. Then, an insulating material layer 14 such as SiO2 or the like is filled into the groove 6 by a low-temperature CVD operation; a device isolation region 7 is formed. By this setup, it is not required to execute a high-temperature heat treatment after this process; the thermal distortion is not caused and an impurity is not distributed again; a characteristic can be stabilized and the reliability can be enhanced. The surface of the substrate is spin-coated with a resin 15; it is etched back; the surface is made flat; after that, a base, an emitter, a metal wiring part and the like (not shown in the figure) are formed by using a well-known method.
JP62206181A 1987-08-19 1987-08-19 Manufacturing method of bipolar transistor Expired - Lifetime JP2615652B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62206181A JP2615652B2 (en) 1987-08-19 1987-08-19 Manufacturing method of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62206181A JP2615652B2 (en) 1987-08-19 1987-08-19 Manufacturing method of bipolar transistor

Publications (2)

Publication Number Publication Date
JPS6449261A true JPS6449261A (en) 1989-02-23
JP2615652B2 JP2615652B2 (en) 1997-06-04

Family

ID=16519156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62206181A Expired - Lifetime JP2615652B2 (en) 1987-08-19 1987-08-19 Manufacturing method of bipolar transistor

Country Status (1)

Country Link
JP (1) JP2615652B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0323649A (en) * 1989-06-21 1991-01-31 Oki Electric Ind Co Ltd Manufacture of semiconductor element
WO2001048814A1 (en) * 1999-12-24 2001-07-05 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943545A (en) * 1982-09-06 1984-03-10 Hitachi Ltd Semiconductor ic device and its manufacture
JPS6080276A (en) * 1983-10-05 1985-05-08 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943545A (en) * 1982-09-06 1984-03-10 Hitachi Ltd Semiconductor ic device and its manufacture
JPS6080276A (en) * 1983-10-05 1985-05-08 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming semiconductor element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0323649A (en) * 1989-06-21 1991-01-31 Oki Electric Ind Co Ltd Manufacture of semiconductor element
WO2001048814A1 (en) * 1999-12-24 2001-07-05 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer

Also Published As

Publication number Publication date
JP2615652B2 (en) 1997-06-04

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