JPS642317A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS642317A
JPS642317A JP15828287A JP15828287A JPS642317A JP S642317 A JPS642317 A JP S642317A JP 15828287 A JP15828287 A JP 15828287A JP 15828287 A JP15828287 A JP 15828287A JP S642317 A JPS642317 A JP S642317A
Authority
JP
Japan
Prior art keywords
region
film
sio
collector
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15828287A
Other languages
Japanese (ja)
Other versions
JPH012317A (en
Inventor
Tsunenori Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62-158282A priority Critical patent/JPH012317A/en
Priority claimed from JP62-158282A external-priority patent/JPH012317A/en
Publication of JPS642317A publication Critical patent/JPS642317A/en
Publication of JPH012317A publication Critical patent/JPH012317A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To make it possible to microscopically form a shallow highly efficient impurity diffusion region in an excellent reproducible manner by a method wherein the surface of the impurity diffusion region is oxidized at the prescribed temperature or below, and then a silicon oxide film is removed.
CONSTITUTION: After an n+ buried layer 2 has been diffused on a p-Si substrate 1, an n-type epitaxial layer (n-collector region 3) is grown, and a p+ element isolation region 4 and n+ collector contact region 5 are formed thereon. Then, a p+ base region 16 is formed by conducting a heat treatment in a nitrogen atmosphere, and the SiO2 film on the surface of the region 16 is removed. Subsequently, an SiO2 film 11 is grown in an oxidizing atmosphere at the temperature of 900°C or below (850°C) by controlling the treatment perios. Then, the film 11 is entirely removed by conducting the prescribed etching. Then, an emitter region 17 is formed, a window is provided on an SiO2 film, and a collector electrode C, an emitter electrode E and a base electrode B are formed.
COPYRIGHT: (C)1989,JPO&Japio
JP62-158282A 1987-06-24 Manufacturing method of semiconductor device Pending JPH012317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-158282A JPH012317A (en) 1987-06-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-158282A JPH012317A (en) 1987-06-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS642317A true JPS642317A (en) 1989-01-06
JPH012317A JPH012317A (en) 1989-01-06

Family

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