JPS6438843A - Information processing system with microprogram controlled arithmetic processor - Google Patents

Information processing system with microprogram controlled arithmetic processor

Info

Publication number
JPS6438843A
JPS6438843A JP63086426A JP8642688A JPS6438843A JP S6438843 A JPS6438843 A JP S6438843A JP 63086426 A JP63086426 A JP 63086426A JP 8642688 A JP8642688 A JP 8642688A JP S6438843 A JPS6438843 A JP S6438843A
Authority
JP
Japan
Prior art keywords
controller
communication
logical
given
microprogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63086426A
Other languages
Japanese (ja)
Inventor
Takashi Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63086426A priority Critical patent/JPS6438843A/en
Publication of JPS6438843A publication Critical patent/JPS6438843A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To resolve the overhead of the processing of a system controller by interrupting the system controller by a communication request means independently of a trouble detection signal. CONSTITUTION:The decoded result of a micro instruction from a decoder 171 is given to a communication information holding means 110. The output of the means 110 is held in the communication information holding means 110. If there are bits of logical '1' in this held information, logical '1' is given to an update suppressing means 120, and internal information in an arithmetic processing means 100 is frozen while this signal of logical '1' is given. In parallel with this freezing operation, the output of an OR circuit 151 interrupts a system controller 200 as a communication request by a communication request means 140. The controller 200 recognizes the interrupt from the means 140 other than that from a trouble reporting means 133. The controller 200 outputs a signal due to a communication release means 150 in response to this interrupt from the means 140 to release the suppression state due to the means 120. Thereafter, the controller 200 starts a microprogram by a microprogram start means 160.
JP63086426A 1987-04-07 1988-04-07 Information processing system with microprogram controlled arithmetic processor Pending JPS6438843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63086426A JPS6438843A (en) 1987-04-07 1988-04-07 Information processing system with microprogram controlled arithmetic processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8372087 1987-04-07
JP63086426A JPS6438843A (en) 1987-04-07 1988-04-07 Information processing system with microprogram controlled arithmetic processor

Publications (1)

Publication Number Publication Date
JPS6438843A true JPS6438843A (en) 1989-02-09

Family

ID=26424760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63086426A Pending JPS6438843A (en) 1987-04-07 1988-04-07 Information processing system with microprogram controlled arithmetic processor

Country Status (1)

Country Link
JP (1) JPS6438843A (en)

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