JPS57207971A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS57207971A
JPS57207971A JP9447581A JP9447581A JPS57207971A JP S57207971 A JPS57207971 A JP S57207971A JP 9447581 A JP9447581 A JP 9447581A JP 9447581 A JP9447581 A JP 9447581A JP S57207971 A JPS57207971 A JP S57207971A
Authority
JP
Japan
Prior art keywords
input
instruction
output instruction
processing
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9447581A
Other languages
Japanese (ja)
Inventor
Hajime Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9447581A priority Critical patent/JPS57207971A/en
Publication of JPS57207971A publication Critical patent/JPS57207971A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Abstract

PURPOSE:To improve the processing capacity of a data processing device, by breaking the execution of an input-output instruction, and interrupting a specified system control instruction which occurs while executing an input-output instruction which requires a relatively long time to be processed. CONSTITUTION:When a prefixed specified system control instruction is decoded by a decode 13, the decoder 13 assigns an interrupt signal 501 having a higher priority against an interruption controlling circuit 14 and makes an interruption request with a higher priority against a sub-processing unit 2 through the circuit 14. Then, in the processing unit 2, a microprogram sequence of an input-output instruction being executed at a controlling circuit 20 is interrupted and an interruption processing routine is started. When a prescribed processing is completed, a completion interruption request against a sub-processing unit 1 is generated at an instruction 204 and the input-output instruction being interrupted is restarted.
JP9447581A 1981-06-18 1981-06-18 Data processing device Pending JPS57207971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9447581A JPS57207971A (en) 1981-06-18 1981-06-18 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9447581A JPS57207971A (en) 1981-06-18 1981-06-18 Data processing device

Publications (1)

Publication Number Publication Date
JPS57207971A true JPS57207971A (en) 1982-12-20

Family

ID=14111296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9447581A Pending JPS57207971A (en) 1981-06-18 1981-06-18 Data processing device

Country Status (1)

Country Link
JP (1) JPS57207971A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205663A (en) * 1983-05-07 1984-11-21 Hitachi Ltd Sequence controller having computer process mode
JPS63132368A (en) * 1986-11-21 1988-06-04 Nec Corp Interrupting system for multiprocessor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5285444A (en) * 1976-01-09 1977-07-15 Agency Of Ind Science & Technol Information processing system
JPS5323534A (en) * 1976-08-18 1978-03-04 Fujitsu Ltd Communication system between sub-systems
JPS5665259A (en) * 1979-11-02 1981-06-02 Hitachi Ltd Interruption control circuit of multiprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5285444A (en) * 1976-01-09 1977-07-15 Agency Of Ind Science & Technol Information processing system
JPS5323534A (en) * 1976-08-18 1978-03-04 Fujitsu Ltd Communication system between sub-systems
JPS5665259A (en) * 1979-11-02 1981-06-02 Hitachi Ltd Interruption control circuit of multiprocessor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205663A (en) * 1983-05-07 1984-11-21 Hitachi Ltd Sequence controller having computer process mode
JPS63132368A (en) * 1986-11-21 1988-06-04 Nec Corp Interrupting system for multiprocessor

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