JPS6425421A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6425421A JPS6425421A JP62181492A JP18149287A JPS6425421A JP S6425421 A JPS6425421 A JP S6425421A JP 62181492 A JP62181492 A JP 62181492A JP 18149287 A JP18149287 A JP 18149287A JP S6425421 A JPS6425421 A JP S6425421A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- etched
- film
- silicon substrate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 238000000034 method Methods 0.000 abstract 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 238000005530 etching Methods 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 238000000151 deposition Methods 0.000 abstract 1
Landscapes
- Drying Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To suppress the concentration of a magnetic field at corner parts by making a lower corner round, thereby performing etching in two steps. CONSTITUTION:After forming an oxide film a2 with a CVD process on a silicon substrate 1, the oxide film a2 is etched by using a resist 3 as the mask of a selective etching. Then, after depositing a PSG film 4 on the oxide film a2 as well as the silicon substrate 1 with the CVD process, the PSG film 4 is etched with an RIE process and its etching allows the PSG film 4 to remain only at the side face of the oxide film a2. Next, after the silicon substrate 1 is etched by using the oxide film a2 as well as the PSG film 4 as masks with the RIE process, the PSG film 4 is removed. Further, when the silicon substrate 1 is etched by using the oxide film a2 as the mask with the RIE process, its etching makes recessed corners round.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62181492A JPS6425421A (en) | 1987-07-21 | 1987-07-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62181492A JPS6425421A (en) | 1987-07-21 | 1987-07-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6425421A true JPS6425421A (en) | 1989-01-27 |
Family
ID=16101704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62181492A Pending JPS6425421A (en) | 1987-07-21 | 1987-07-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6425421A (en) |
-
1987
- 1987-07-21 JP JP62181492A patent/JPS6425421A/en active Pending
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