JPS6425421A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6425421A
JPS6425421A JP62181492A JP18149287A JPS6425421A JP S6425421 A JPS6425421 A JP S6425421A JP 62181492 A JP62181492 A JP 62181492A JP 18149287 A JP18149287 A JP 18149287A JP S6425421 A JPS6425421 A JP S6425421A
Authority
JP
Japan
Prior art keywords
oxide film
etched
film
silicon substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181492A
Other languages
Japanese (ja)
Inventor
Hiroyuki Kaimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62181492A priority Critical patent/JPS6425421A/en
Publication of JPS6425421A publication Critical patent/JPS6425421A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To suppress the concentration of a magnetic field at corner parts by making a lower corner round, thereby performing etching in two steps. CONSTITUTION:After forming an oxide film a2 with a CVD process on a silicon substrate 1, the oxide film a2 is etched by using a resist 3 as the mask of a selective etching. Then, after depositing a PSG film 4 on the oxide film a2 as well as the silicon substrate 1 with the CVD process, the PSG film 4 is etched with an RIE process and its etching allows the PSG film 4 to remain only at the side face of the oxide film a2. Next, after the silicon substrate 1 is etched by using the oxide film a2 as well as the PSG film 4 as masks with the RIE process, the PSG film 4 is removed. Further, when the silicon substrate 1 is etched by using the oxide film a2 as the mask with the RIE process, its etching makes recessed corners round.
JP62181492A 1987-07-21 1987-07-21 Manufacture of semiconductor device Pending JPS6425421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181492A JPS6425421A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181492A JPS6425421A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6425421A true JPS6425421A (en) 1989-01-27

Family

ID=16101704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181492A Pending JPS6425421A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6425421A (en)

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