JPS6421944A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6421944A
JPS6421944A JP17934187A JP17934187A JPS6421944A JP S6421944 A JPS6421944 A JP S6421944A JP 17934187 A JP17934187 A JP 17934187A JP 17934187 A JP17934187 A JP 17934187A JP S6421944 A JPS6421944 A JP S6421944A
Authority
JP
Japan
Prior art keywords
insulating film
interlayer insulating
smoothing
exposed
coating solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17934187A
Other languages
Japanese (ja)
Inventor
Koichi Sumiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17934187A priority Critical patent/JPS6421944A/en
Publication of JPS6421944A publication Critical patent/JPS6421944A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible to harden SOG at a low temperature as well as to make a through hole easily by a method wherein the upper surface of an interlayer insulating film is exposed by the etching with which heat is generated on the step-smoothing coating solution applied to the interlayer insulating film, and the step-smoothing solution applied to the stepped part is hardened. CONSTITUTION:A step-smoothing solution 5 is applied to the interlayer insulating film 4 covering the lower layer wiring 3 on a semiconductor element in such a manner that a stepped part is filled up. An etching treatment with which heat will be generated on the step-smoothing coating solution is conducted, the upper surface of the interlayer insulating film 4 is exposed, and the step- smoothing coating solution 5 coated to said stepped part is hardened. Subsequently, a through hole 6 reaching the lower wiring 3 is perforated on the exposed interlayer insulating film 4, and an upper layer wiring 7 contacting to the lower wiring 3 is formed through the intermediary of the through hole 6. For example, the SOG as the above-mentioned step-smoothing coating solution is applied to the interlayer insulating film 4, then the SOG 5 is etched using an Ar<+> ion beam, and the upper surface of the interlayer insulating film 4, in which the through hole 6 is made, is exposed.
JP17934187A 1987-07-16 1987-07-16 Manufacture of semiconductor device Pending JPS6421944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17934187A JPS6421944A (en) 1987-07-16 1987-07-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17934187A JPS6421944A (en) 1987-07-16 1987-07-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6421944A true JPS6421944A (en) 1989-01-25

Family

ID=16064148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17934187A Pending JPS6421944A (en) 1987-07-16 1987-07-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6421944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990051680A (en) * 1997-12-19 1999-07-05 김영환 Method of forming multilayer wiring of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990051680A (en) * 1997-12-19 1999-07-05 김영환 Method of forming multilayer wiring of semiconductor device

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