JPS57210671A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57210671A
JPS57210671A JP9376381A JP9376381A JPS57210671A JP S57210671 A JPS57210671 A JP S57210671A JP 9376381 A JP9376381 A JP 9376381A JP 9376381 A JP9376381 A JP 9376381A JP S57210671 A JPS57210671 A JP S57210671A
Authority
JP
Japan
Prior art keywords
recess
film
covered
etching
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9376381A
Other languages
Japanese (ja)
Other versions
JPH0370385B2 (en
Inventor
Masamizu Konaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9376381A priority Critical patent/JPS57210671A/en
Publication of JPS57210671A publication Critical patent/JPS57210671A/en
Publication of JPH0370385B2 publication Critical patent/JPH0370385B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form a flat field oxidized film by forming a recess on a semiconductor substrate, convering an insulating film on the overall surface, burying by etching an insulating film in the recess, further covering an insulating film and uniformly etching the surface. CONSTITUTION:A thermally oxidized film 2 and an aluminum layer are covered on the surface of an Si substrate 1, and a region to become a field part is then etched, thereby forming a recess. Subsequently, ions are implanted for preventing an inversion to the recess, and a CVD SiO2 film 6 is covered in a sufficient thickness on the overall surface. Then, the film 6 is etched by using a selective etching method having an etching speed faster than the other part at the side surface, and is buried in the recess. At this time. a V-shaped groove 7 remains in the periphery of the recess. Thereafter, a CVD SiO2 film 8 is covered again on the overall surface, a resist 9 is covered on the surface, and ion etching is uniformly performed. Then, the film 8 is buried in the groove 7, thereby flattening the surface.
JP9376381A 1981-06-19 1981-06-19 Manufacture of semiconductor device Granted JPS57210671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9376381A JPS57210671A (en) 1981-06-19 1981-06-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9376381A JPS57210671A (en) 1981-06-19 1981-06-19 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57210671A true JPS57210671A (en) 1982-12-24
JPH0370385B2 JPH0370385B2 (en) 1991-11-07

Family

ID=14091464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9376381A Granted JPS57210671A (en) 1981-06-19 1981-06-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57210671A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59178773A (en) * 1983-03-30 1984-10-11 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59178773A (en) * 1983-03-30 1984-10-11 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0370385B2 (en) 1991-11-07

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