JPS6421785A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6421785A
JPS6421785A JP62176890A JP17689087A JPS6421785A JP S6421785 A JPS6421785 A JP S6421785A JP 62176890 A JP62176890 A JP 62176890A JP 17689087 A JP17689087 A JP 17689087A JP S6421785 A JPS6421785 A JP S6421785A
Authority
JP
Japan
Prior art keywords
reference clock
outputting means
outputted
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62176890A
Other languages
Japanese (ja)
Inventor
Yoshihiro Shibuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP62176890A priority Critical patent/JPS6421785A/en
Publication of JPS6421785A publication Critical patent/JPS6421785A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To easily eliminate the delay of an outputting means for an inputting means by adding two sets of input simultaneous outputting means, synchronizing with a reference clock, to a customary semiconductor storage device. CONSTITUTION:A multi-input simultaneous outputting means 1 and the multi- input simultaneous outputting means 2, which synchronize with the reference clock CL, are added. Accordingly, a signal 12, outputted from a memory array cell controlling means 4, and the signal 14, outputted from a memory array cell 3, can be respectively limited within one period of the reference clock CL, in respect of their delays. Thus, the output having no delay for the reference clock CL, can be outputted from the outputting means 16.
JP62176890A 1987-07-15 1987-07-15 Semiconductor integrated circuit device Pending JPS6421785A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62176890A JPS6421785A (en) 1987-07-15 1987-07-15 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62176890A JPS6421785A (en) 1987-07-15 1987-07-15 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6421785A true JPS6421785A (en) 1989-01-25

Family

ID=16021546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62176890A Pending JPS6421785A (en) 1987-07-15 1987-07-15 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6421785A (en)

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