JPS6417290A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6417290A
JPS6417290A JP62172190A JP17219087A JPS6417290A JP S6417290 A JPS6417290 A JP S6417290A JP 62172190 A JP62172190 A JP 62172190A JP 17219087 A JP17219087 A JP 17219087A JP S6417290 A JPS6417290 A JP S6417290A
Authority
JP
Japan
Prior art keywords
circuit
detecting
latching
output buffer
malfunction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62172190A
Other languages
Japanese (ja)
Inventor
Takao Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62172190A priority Critical patent/JPS6417290A/en
Publication of JPS6417290A publication Critical patent/JPS6417290A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To prevent the generation of a malfunction by detecting an operation period of an output buffer circuit, and applying a latch automatically to a part of a circuit in a device only in its period. CONSTITUTION:The titled device is provided with a detecting circuit 6 for detecting an operation period of an output buffer circuit 2, and a latching circuit 3 for latching a data signal by an output of this detecting circuit 6 and separating a storage element part 4 and an external circuit. In this state, in the output buffer circuit 2 and the operation detecting circuit 6, operations in each output buffer are detected and they are synthesized in a synthesizing circuit 9 and inputted to the latching circuit 3. In the latching circuit 3, the input buffer circuit 2 and the storage element part 4 are separated in a period in which a malfunction is executed, and also, a correct signal is held. In such a way, it can be prevented that the malfunction of the input buffer circuit 2 is propagated to the whole device.
JP62172190A 1987-07-10 1987-07-10 Semiconductor storage device Pending JPS6417290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62172190A JPS6417290A (en) 1987-07-10 1987-07-10 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172190A JPS6417290A (en) 1987-07-10 1987-07-10 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6417290A true JPS6417290A (en) 1989-01-20

Family

ID=15937244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172190A Pending JPS6417290A (en) 1987-07-10 1987-07-10 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6417290A (en)

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