JPS6489617A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6489617A
JPS6489617A JP62247611A JP24761187A JPS6489617A JP S6489617 A JPS6489617 A JP S6489617A JP 62247611 A JP62247611 A JP 62247611A JP 24761187 A JP24761187 A JP 24761187A JP S6489617 A JPS6489617 A JP S6489617A
Authority
JP
Japan
Prior art keywords
data
output
dvc1
goes
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247611A
Other languages
Japanese (ja)
Inventor
Takayuki Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62247611A priority Critical patent/JPS6489617A/en
Publication of JPS6489617A publication Critical patent/JPS6489617A/en
Priority to US07/711,571 priority patent/US5367485A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To easily execute the common connection of plural devices by connecting a latch circuit, which is inverted by an output from an output edge, to the output terminal of a three-state output circuit. CONSTITUTION:When an OE1 signal of a device(Dvc) 1 goes to be a low level at a time T1 in a semiconductor device, either transistors(Tr) 1 or 2 goes to be a low resistance and output data 'D1' of the Dvc1 is outputted. Thus, respective latches 20 of the Dvc1 and a DVc2 are forcibly inverted so as to be the same logical value as the data 'D1'. The OE1 signal of the Dvc1 goes to a high level condition at a time T2 and the Tr 1 and the Tr2 go to a high resistance condition, however, the data 'D1' are latched and since outputs 14 and 16 hold the 'D1', a synthesizing output holds the 'D1'. After a time T3, the same operation as the operation at the times T1 and T2 to the data 'D1' is repeated to data 'D2', 'D3' and so on. Thus, without paying special attention to the timing of the OE signal, the common connection of the plural devices can be easily executed.
JP62247611A 1987-09-29 1987-09-29 Semiconductor device Pending JPS6489617A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62247611A JPS6489617A (en) 1987-09-29 1987-09-29 Semiconductor device
US07/711,571 US5367485A (en) 1987-09-29 1991-06-03 Semiconductor memory device including output latches for improved merging of output data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247611A JPS6489617A (en) 1987-09-29 1987-09-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6489617A true JPS6489617A (en) 1989-04-04

Family

ID=17166081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247611A Pending JPS6489617A (en) 1987-09-29 1987-09-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6489617A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07281918A (en) * 1994-04-13 1995-10-27 Nec Corp Switching circuit for duplex signal relay system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925419A (en) * 1982-08-02 1984-02-09 Hitachi Ltd Cmos integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925419A (en) * 1982-08-02 1984-02-09 Hitachi Ltd Cmos integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07281918A (en) * 1994-04-13 1995-10-27 Nec Corp Switching circuit for duplex signal relay system

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