JPS6387771A - Field effect transistor - Google Patents

Abstract

PURPOSE:To improve high frequency characteristics and breakdown strength by preparing an N-type island region and at the same time making the thickness of an insulating film below a gate electrode thinner than those of insulating films at other parts. CONSTITUTION:Even though an arrangement of a N-type island region 7 makes P-type regions 5 and 5' deeper, it also makes a length between N-type source regions 6 and 6' of P-type base regions 5 and 5' that result in a real channel region below a gate electrode 9 and the N-type island region 7 shorter and further, makes a part below the N-type source regions 6 and 6' of the P-type regions 5 and 5' thicker. Since the real channel region is short and lower of the N-type source regions 6 and 6' of the p-type regions 5 and 5' can be thicker, the inner resistance can be reduced to obtain favorable high frequency characteristics. Subsequently, it is difficult for a depletion layer developed from the P-type regions 5 and 5' in the N-type island region 7 but the gate electrode 9 is so located on the island region 7 that it is easy for the depletion layer to extend in the island region. Then, in addition to permitting a drain current to be taken out by passing through the P-type regions 5 and 5', the above arrangement makes it possible to perform high breakdown strengthening.

Description

[Detailed description of the invention] The present invention relates to field effect transistors.

Field-effect transistors inherently have excellent frequency characteristics and are also thermally stable, allowing them to provide excellent performance for high-frequency, high-output applications.

As an example of a field effect transistor, a structure in which charges flow in the thickness direction of a semiconductor substrate has been proposed. For example, a NW conductor substrate or an epitaxial layer is provided with opposing portions of Pm layers serving as base regions, and N-type layers serving as source regions are formed in opposing portions of the Pm layers, respectively. A gate electrode is formed on the region between the Nu layers via a gate oxide film. The drain electrode is formed directly on the back side of the semiconductor substrate. The field-effect transistor by Motokiri has a small feedback capacitance between the gate electrode and the drain electrode, and has excellent high frequency characteristics.The drain electrode is taken out from the back side of the semiconductor substrate, so it can withstand high voltage.
Suitable for high power applications.

However, the disadvantage of this structure is that in order to further reduce the feedback capacitance, it is necessary to make the P-type layer deeper, which inevitably increases the distance between the N-type semiconductor substrate and the N-type region that is the source region. The channel length under the electrode becomes longer.

This results in a change in frequency characteristics, an increase in internal resistance, and a decrease in the output that can be extracted. In addition, in order to shorten the channel length under the gate electrode, the source region N
When the mold layer is formed deep, the base region pmi
The portion under the positive N-type layer becomes thinner, which also increases the internal resistance and deteriorates the frequency characteristics.

An object of the present invention is to obtain a field effect transistor with excellent high frequency characteristics and high breakdown voltage.

According to the present invention, - led [! a semiconductor substrate, a first region of another conductivity type formed on the surface of this semiconductor substrate and having portions facing each other at a predetermined interval; a second region of the semiconductor substrate with a -conductor formed on the surface of the semiconductor substrate between the opposing portions of the first region; (1) which is continuously formed on the first region and the third region between the regions with an insulating film interposed therebetween. ffl, a source electrode connected to the second region, and a drain electrode formed on the semiconductor substrate.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows an N-type St epitaxial wafer. N+
type high impurity concentration substrate 1 (e.g. N = 10" at
oms/cl/I or more) on top of the N-type epitaxial layer 2
(N = 10” to 11014 atoms, thickness is several μ
The number of microorganisms has been increased to about 100,000 or more. A mask layer 3 (for example, a thermal oxide film, etc.) for impurity diffusion is formed on this epitaxial wafer, and further holes 12, 12' are partially opened.
, do 13. The openings 12 and 12' are in the shape of a ring or a comb, and are continuous with each other.

The illustrated length a is approximately several microns, and the length b is approximately several microns to several tens of microns, and b) is 2 m.

As shown in FIG. 2, a mask layer 4 is selectively formed over the opening 13 in an ion implantation or impurity diffusion process.

81. The material of the mask layer 4 is different from that of the mask layer 3, and the mask layer 4 can be selectively removed (for example, photoresist); 81. N4 etc.) is used. In this step, the alignment error only needs to be 1 or less in length, and there is no problem with conventional manufacturing techniques. Thereafter, the depth of the P-type region 5 is formed on the order of several μm by ion implantation or diffusion to form the P-type region 5 or by subsequent thermal diffusion. This depth roughly corresponds to the channel length.

Next, as shown in FIG. 3, after mask layer 4 is removed, N-type impurities are introduced by ion implantation or diffusion to form high impurity concentration regions 6,6' and 7. territoryfiR6,6'
is the source region, and region 7 is the island region. Area 6
, 6- and 7 corresponds to the channel length L1, and can be made from about several microns to 1 micron or less.

Thereafter, a gate insulating film 8 of a predetermined thickness is continuously formed on a region including the surface portions of regions 5 and 5- between regions 6 and 6' and 7, specifically, on the surface region between regions 6 and 6I. form,
Furthermore, electrodes 9tlO+11 are formed, respectively, and the element shown in FIG. 4 is formed. Other details are explained in the conventional MO
It is omitted because it can be easily inferred from the manufacturing method of S FET. Here, electrode 9 is a gate electrode, 10 is a sonis electrode, and 11 is a drain electrode.

The source electrode 10 has N-type regions 6, 6' and 2-ri regions 5.5'.
are in continuous contact with.

According to this structure, by providing the N-type island region 7, even if the P-type regions 5, 5' are made deep, the N-type source of the P-type base region 5.51, which becomes a substantial channel region under the gate electrode 9, Regions 6, 6' and N-type island region 7
It is possible to shorten the length between the P-type regions 5 and 5I, and thicken the portions of the P-type regions 5 and 5I below the N-type source regions 6 and 6'. The substantial channel region is short and the NW of P-type regions 5, 5'
Since the area below the source region 6.61 can be made thicker, the internal resistance can be reduced and good high frequency characteristics can be obtained. In addition, in the N deaf island area 7, the P type area 5.5
The depletion layer from ' is revived, but on top of it
There is a lot that can be achieved. It is obvious that what is described for the N-channel type is also completely applicable to the P-channel type.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. 1...N jl semiconductor substrate, 2...N type epitaxial layer, 3.4...mask layer, 5,5r...
P type layer, 6.6'... N type layer, 7... Island region, 8... Gate oxide film, 9... Gate 1
E electrode, 10... Source electrode, 11... Drain electrode 1st and 2nd

Claims (3)

[Claims] (1) a semiconductor substrate of one conductivity type; a first region of another conductivity type having portions formed on the surface of the semiconductor substrate that face each other at a predetermined interval; the second region of the one conductivity type formed in each portion, and the impurity concentration higher than that of the semiconductor substrate of the one conductivity type formed on the surface of the semiconductor substrate between the opposing portions of the first region; a third region, a gate electrode continuously formed on the first region and the third region between the second regions via an insulating film, and connected to the second region. A field effect transistor comprising a source electrode and a drain electrode formed on the semiconductor substrate. (2) The field effect transistor according to claim 1, wherein the source electrode is connected to the first and second regions. (3) The field effect transistor according to claim 1, wherein the insulating film under the gate electrode is thinner than other parts of the insulating film.