JPS62137870A - Manufacture of mis transistor - Google Patents

Abstract

PURPOSE:To reduce the quantity of minority carrier to be injected onto a substrate from a source region, to reduce source resistance and to increase trans- conductance by a method wherein a low resistance source region is formed between a Schottky junction and the channel region of a transistor. CONSTITUTION:First, a field oxide film 12, a gate oxide film 13 and an N<+> type polycrystalline silicon gate 13 are successively formed on an N-type silicon substrate 11. Then, after a silicon nitride film has been deposited on the substrate 11, an anisotropic etching is performed, and a silicon nitride film spacer 15 is left on the side wall of the gate 14. Subsequently, a thin film of molybdenum, for example, is deposited on the substrate, and after molybdenum silicide has been formed by performing a heat treatment, non-reaction molybdenum is selectively removed, and a Schottky-junction source/drain region 161 and a gate resistance layer 162 are formed. Then, oxide films 181 and 182 are formed on the regions 161 and 162, the spacer 15 is selectively removed, and boric ions are implanted into the substrate using the oxide films 181 and 182 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing MIS transistors.

Conventional technology complementary MIS integrated circuits are characterized by low power consumption, but because both N-channel and P-channel transistors are formed on the same substrate, they are inevitably constructed with a PNPN structure, that is, a thyristor. This has the disadvantage that there is a possibility that so-called love bubbles may occur, which may turn on due to an external surge or the like.

One measure to prevent love bubbles is to make the source region of the MIS transistor, which serves as the gate of the thyristor, a Schottky junction instead of a Pn junction to suppress the injection of minority carriers.

Conventionally, the method for manufacturing an M, IS) transistor whose source region is a Schottky junction as described above is as shown in FIGS. 3(a) to (3).
It was a method of forming through a process cross-sectional view as shown in C).

First, as shown in FIG. 3(a), an n-type silicon substrate 1
A field oxide film 2, a gate oxide film 3, and a polycrystalline silicon gate 4 are sequentially formed thereon.

Next, after depositing an oxide film on the entire surface of the substrate by a method such as C'/D, anisotropic etching is performed to form spacers on the side walls of the polycrystalline silicon gate 4, as shown in FIG. 3(b). form 5.

Next, a platinum film (not shown) is deposited on the entire surface of the substrate, heat-treated to cause the platinum film to react with silicon, and the unreacted platinum film is removed by etching, as shown in FIG. 3(C). Platinum silicide layers 61 and 62 are selectively formed on n-type silicon substrate 1 and polycrystalline silicon gate 4 in this manner.

The n-type silicon substrate 1 generally has an impurity concentration of about 10 ff or less, and forms a Schottky junction with the platinum silicide layer 61. Further, since the polycrystalline silicon gate 4 is generally doped to a high concentration of about 10 t7n , an ohmic contact is made between the polycrystalline silicon gate 4 and the platinum silicide layer 62 . Here, the spacer 6 serves to prevent electrical short circuits between the platinum silicide layers 61 and 62.

Problems to be Solved by the Invention [2] An enlarged sectional view of the main part of the transistor formed by the conventional MIS transistor manufacturing method as described above is shown in FIG. The reaction between platinum and silicon that forms the platinum silicide layer 61 is regulated at the edges of the spacer 6 and gate oxide film 3 and hardly progresses in the lateral direction, so it does not reach the channel region directly under the gate 7. do not have.

Therefore, at the end of the channel region 7, a polycrystalline silicon/ge-
(4) well controlled by No high resistance region 71
Since the so-called gate offset portion 1 remains and this high resistance region element 1 exists, there is a problem that the mutual conductance of the transistor is significantly lowered, and the current driving ability is also lowered.

The present invention solves these problems, and because the source region is a Schottky junction, the amount of minority carriers injected into the substrate is small, and a low-resistance source region is provided between the Schottky region and the channel region. This provides a method for manufacturing a MIS l-ra/registor with large mutual conductance.

Means for solving the problems (MIS of the present invention for solving the above problems)
The method for manufacturing a transistor includes the following steps: - selectively forming an oxidation-resistant film on the sidewalls of a gate formed on a semiconductor substrate having a conductivity type; a step of forming a metal compound layer forming a Schottky junction with respect to the metal compound; a step of selectively etching away the oxidation-resistant film after oxidizing the surface of the metal compound to form an oxide film; and a step of selectively etching away the oxidation-resistant film; The step of introducing impurities of opposite conductivity type into the semiconductor substrate using the oxide film as a mask.

Function: According to this MIS transistor manufacturing method, most of the source region becomes a Schottky junction, so minority carrier injection into the substrate can be controlled, and latch-up can therefore be prevented when a complementary MIS integrated circuit is constructed. . Furthermore, since a low-resistance source region can be formed between the Schottky junction and the channel region of the transistor, an MIS transistor with low source resistance and high mutual conductance can be obtained.

Embodiment FIGS. 1(a) to 1(0) are step-by-step sectional views showing an embodiment of a method for manufacturing an MIS transistor of the present invention.

First, as shown in FIG. 1(a), an N-type silicon substrate 1
1, a field oxide film 12, a gate oxide film 13, N+
The molded crystal silicon gates 14 are sequentially formed, and the N
The surface of the mold silicon substrate 11 exposes the region where the source/drain is to be formed. At this time, the surface of the N-type silicon substrate 11 does not necessarily need to be exposed in the source/drain formation region 21.

Next, a silicon nitride film is deposited on the entire surface of the N-type silicon substrate 11 to a thickness of about 100 to 400 nm, and then anisotropic etching is performed on the entire surface to form an N+ A silicon nitride film spacer 16 is left on the side wall of the molded crystalline silicon gate 14. At this time, in the source/drain formation region 21, the N-type silicon substrate 11
surface must be exposed. Further, the upper surface of the N+ type polycrystalline silicon gate 14 does not necessarily have to be exposed.

Next, a thin film of a metal such as molybdenum, whose silicide forms a Schottky junction with N-type silicon, is deposited on the entire surface of the substrate to a thickness of several tens to 1,100 nanometers, and then deposited in an inert gas atmosphere. After heat treatment to form molybdenum silicide, unreacted molybdenum is selectively etched away to form a Schottky junction source/drain region 161 and an on-gate resistive layer 16, as shown in FIG. 1(C).
2. Note that at the time of Figure 1 (1)), N″-
If the upper surface of the polycrystalline silicon gate 14 is not exposed, the over-gate low resistance layer 162 is not formed.

Next, the entire substrate is heat-treated in an oxidizing atmosphere to form oxide films 181 and 182 on the Sigitky junction source/drain region 161 and on the gate low resistance layer 162 at a 1000 nm as shown in FIG. 1(d). It is formed to a thickness of about 200 nm. At this time, the side walls of the N+ type polycrystalline silicon gate 14 are not oxidized unless they are washed away by the silicon nitride film spacer 15.

Then, as shown in FIG. 1(6), the silicon nitride film scrubber 15 is selectively removed by a method such as C sotoisozing using phosphoric acid. .

Next, as shown in FIG. 1(f'), the oxide films 181 and 182 are used as a mask 7, and a 1000-degree film is placed in the N-type silicon substrate.
Boron ions of about 14 to 1 oj5, -, -2 are implanted to form P-type source/drain regions 19.

Thereafter, the process may be carried out according to the usual method for manufacturing a MOS (MOS) lanogistor.

The structure of the M□S) transistor manufactured according to the second embodiment will be explained in more detail.

FIG. 2 is a sectional view showing a main part of the MQS transistor manufactured according to an embodiment of the present invention shown in FIGS. 1(a) and 1(r). Most of the area of the source-substrate junction is occupied by the junction between the Schottky junction source/drain region 161 and the N-type silicon substrate 11, and therefore, carriers from the source into the substrate, that is, holes in this case, Few injections occur. In addition, channel region 1
The so-called gate offset portion between 7 and the Schottky junction source/drain region 161 is connected by the P-type source/drain region 19, so that no high resistance region is formed. Therefore, the source resistance is small and the transconductance is large.

In this example, a MOS transistor, that is, a case where the gate insulating film is an oxide film, is shown, but this is a so-called MIS transistor in which a silicon nitride film, other insulating films, or a multilayer film thereof is used as the gate insulating film. ) It is clear that the method can be widely applied to transistors in general.

In addition to the P-channel transistor shown in the above embodiment, it is also possible to use an N-channel transistor by using a P-type substrate and appropriately selecting a metal for forming a Schottky junction.
It can also be applied to transistors. Furthermore, in addition to silicon, the substrate is GaAS.

It goes without saying that the same effect can be obtained by using a compound semiconductor such as InP.

Effects of the Invention As described above, according to the method for manufacturing an MIS transistor of the present invention, it is possible to manufacture an MIS transistor in which the amount of minority carriers injected from the source to the substrate is small, the source resistance is small, and the mutual conductance is large.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of seven steps in accordance with an embodiment of the method for manufacturing an MIS transistor of the present invention, and FIG. FIG. 3 is a cross-sectional view of a main part of a transistor. 11...nW recon board, 12...
Field oxide film, 13... Gate oxide film, 1
4...N+ type polycrystalline silicon gate, 15...
... Silicon nitride film, 161 ... Schottky junction source/drain region, 181 ... Oxide film, 19 ... P type source/drain region. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 13-1-GeF oxide film A 1 Figure '1 back [Nose drain region?
2 Figure 2 Figure 3

Claims (1)

[Claims] After forming a gate insulating film and a gate electrode on a semiconductor substrate having one conductivity type, and selectively forming an oxidation-resistant film on the sidewalls of the gate electrode, a source formation region on the semiconductor substrate is formed. a step of selectively forming a metal compound forming a Schottky junction, a step of oxidizing the surface of the metal compound to form an oxide film, and then selectively etching away the oxidation-resistant film; a step of introducing an opposite conductivity type impurity into the semiconductor substrate using an oxide film as a mask.