JPH0411740A - Manufacture of vertical-type mos field-effect transistor - Google Patents

Abstract

PURPOSE:To increase a breakdown strength in a well region and to improve a load-resistant amount by a method wherein, after the well region is formed, a high-concentration region is formed selectively at the bottom of the well region by a high-energy ion implantation method. CONSTITUTION:An N<-> type epitaxial layer 2 is grown on the surface of an N<+> type semiconductor substrate 1; after that, an oxide film 3 is formed on its surface; a window 3a is opened in the film 3. Then, a P-type well region 4 is formed by making use of it as a mask; after that, a resist 5 is formed; the resist at the part of the window 3a is removed; high-energy ions are implanted through the window 3a; an N<+> region 6 is formed at the bottom of the region 4, i.e., at the boundary part to the layer 2. Since the high- concentration N<+> region exists at a P-N junction part of the region 4 to the layer 2, a breakdown strength at the region 4 is enhanced, and electric current hardly flows to an N<->-P-N<+> parasitic transistor constituted of the layer 2, the region 4 and an N<+> type source region 10, and a load-resistant amount is enhanced. Thereby, a breakdown strength is increased at a well region and the load-resistant a mount can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a vertical MOS field effect transistor (FET).

[Conventional technology]

The conventional manufacturing method of this type of vertical MOSFET is shown in Figure 3 (
Shown in a) to FIG. 3(d). First, as shown in FIG. 3(a), an N epitaxial layer 2 is grown on an N-type semiconductor substrate 1, and an insulating film 3 is formed on the surface of the N-type semiconductor substrate 1 with a thickness of 8,000 to 2 μm.
m form. A window 3a is formed in the insulating film 3 using photolithography, and a P-type impurity is introduced through the window 3a to form a P-type well region 4 to a depth of 3 to 5 μm.

Next, as shown in FIG. 3(b), after removing the insulating film 3, 500 to 2,000 gate insulating films 7 are formed, and 6,000 gate polysilicon films 8 are grown thereon using photolithography. and butter it into a predetermined shape. Then, using this gate polysilicon 8, a P type impurity is introduced to form a P type base region 9.

Thereafter, as shown in FIG. 3(C), a selective diffusion method using photolithography technology, which will not be described further, is applied to form an N'-type source region 10 and a P'-type pack gate in the P-type base region 9. lJl region 11 is formed.

Then, as shown in FIG. 3(d), a glabellar insulating film 12 with a thickness of 5,000 to 1 μm is formed, and a contact window 12a is formed thereon by photolithography. Then, the source electrode 13 is formed of aluminum with a thickness of about 1 to 5 μm, for example. Further, a drain electrode 14 is formed on the back surface of the N'' type semiconductor substrate 1.

[Problem to be solved by the invention]

By the way, in a vertical MOSFET with such a configuration, P
Since the type base region 9 and the P-type well region 4 are close to a one-sided stepped junction, the breakdown voltage thereof is determined by the concentration of the N- type epitaxial layer 2. Since the concentration of this N-type epitaxial layer 2 is low, there is a limit to increasing the withstand voltage. There is a problem in that current tends to flow between the -N'' type source regions 10, and this parasitic transistor is easily turned on, resulting in a decrease in load withstand capacity.

The object of the present invention is to provide a vertical MOSFE with increased load capacity.
An object of the present invention is to provide a method for manufacturing T.

[Means to solve the problem]

The method for manufacturing a vertical MOSFET of the present invention includes the steps of forming a well region of an opposite conductivity type in a semiconductor substrate of one conductivity type, and a high concentration region of one conductivity type at the bottom of the well region by high-energy ion implantation. a step of selectively forming a gate insulating film and a gate electrode in a desired pattern on the surface of the semiconductor substrate; a step of forming a base region of an opposite conductivity type in the well region; forming a source region of one conductivity type.

Furthermore, preferably, after the step of forming the high concentration region of one conductivity type, the method includes a step of forming a high concentration region of the opposite conductivity type directly above the high concentration region.

[Effect]

In the vertical MOSFET manufactured by the method of the present invention, since a high concentration region exists at the junction between the well region and the semiconductor substrate, the withstand voltage in the well region is increased and the load withstand capacity is improved.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are vertical cross-sectional views showing an embodiment of the manufacturing method of the present invention in the order of steps.

Note that an example in which the present invention is applied to an N-channel MOSFET is shown here.

First, as shown in FIG. 1(a), an N-type semiconductor substrate 1 is
An N-type epitaxial layer 2 is grown on the surface of the epitaxial layer 2, and an insulating film 3 is formed on the surface of this epitaxial layer 2 with a thickness of 8,000 to 2 μm.
Form. After opening a window 3a in this insulating film 3, a P-type impurity is introduced using the window 3a as a mask to form a P-type well region 4.

After that, as shown in FIG. 1(b), a resist 5 is formed,
After removing the resist in the window 3a, high-energy ions are implanted through the window 3a to form an N' region 6 at the bottom of the P-type well region 4, that is, at the boundary with the N-type epitaxial layer 2. do. This high-energy ion implantation method is performed at an energy of, for example, 500 eV to 2 MeV.

Next, as shown in FIG. 1(c), after the insulating film 3 is removed, a gate insulating film 7 is formed again to a thickness of 500 to 2000 nm, and a gate polysilicon 8 is formed to a thickness of 6000 nm. , and these are formed into a required pattern to serve as a gate insulating film and a gate electrode, respectively. moreover,
Using the formed gate polysilicon 8 as a mask, P type impurities are introduced to form a P type base region 9.

Thereafter, as shown in FIG. 1(d), the N-type source region 10. A P' type hack gate region 11 is formed.

Then, as shown in FIG. 1(e), an interlayer insulating film 12 is formed to a thickness of 5,000 to 500 mm, a contact hole 12a is formed therein, and a source electrode 13 is formed to a thickness of 1 to 5 μm.
Form to a thickness of . Further, a drain electrode 14 is formed on the back surface of the N-type semiconductor substrate l.

According to the vertical MOSFET formed as shown in FIG.
'' region 6 exists, the withstand voltage in the P-type well region 4 is improved.

Therefore, N--P-N composed of N-type epitaxial layer 2-P-type well region 4-N'' source region 10
``It becomes difficult for current to flow through the parasitic transistor, and the load withstand capability is improved.

FIG. 2 shows another embodiment of the present invention, and FIG.
) is a vertical cross-sectional view of a semiconductor device manufactured by adding a new process after the process.

That is, immediately after the process shown in FIG. 1(b), P-type impurities are introduced by high-energy ion implantation of 500 KeV to 2 MeV using the resist 5 as it is, so that a P-type impurity is introduced directly above the N-type region 6 formed just before. A P-type region 15 is formed.

By adding this step, the P-type well region 4 and the N-
N″ region 6 and P at the PN junction with type epitaxial layer 2
A P''N'' junction consisting of the ''region 15'' is formed, and the withstand voltage of the P-type well region 4 is determined by this P''N'' junction, making it possible to further improve the load withstand capacity described above.

Note that although the above embodiments have shown examples in which the present invention is applied to N-channel MOSFETs, P-channel MOSFETs
Needless to say, the same applies to ET.

〔Effect of the invention〕

As explained above, the present invention creates a high concentration region at the bottom of the well region by introducing impurities of the same conductivity type as the substrate into the semiconductor substrate at a high concentration by high-energy ion implantation after forming the well region. This high-concentration region can be formed selectively, and the withstand voltage in the well region can be increased, making it possible to manufacture a vertical MOSFET with improved load withstand capacity.

In addition, by introducing impurities of the same conductivity type as the well region at a high concentration after forming the high concentration region, a high concentration PN junction can be formed at the bottom of the well region, further increasing the breakdown voltage in the well region. It is possible to manufacture a vertical MOSFET with increased load capacity and improved load capacity.

[Brief explanation of the drawing]

1(a) to e) are longitudinal cross-sectional views showing a manufacturing method according to an embodiment of the present invention in the order of steps; FIG. 3(a) to 3(d) are joint cross-sectional views showing the conventional manufacturing method in the order of steps. DESCRIPTION OF SYMBOLS 1...N゛゛semiconductor substrate, 2...N-type epitaxial layer, 3...Insulating film, 4...P-type melting region, 5
...Resist, 6...N'' region 7... Gate insulating film, 8... Gate polysilicon, 9... P type base region, 10... N'' source region, 11... P゛゛hack gate region, 12... interlayer insulating film, 13...
Source electrode, 14...Drain electrode, 15...P' region (Figure 2)

Claims (1)

[Claims] 1. A step of forming a well region of an opposite conductivity type in a semiconductor substrate of one conductivity type, and selectively forming a high concentration region of one conductivity type at the bottom of the well region by high-energy ion implantation. forming a gate insulating film and a gate electrode in a required pattern on the surface of the semiconductor substrate; forming a base region of opposite conductivity type in the well region; and forming a base region of one conductivity type in the base region. 1. A method for manufacturing a vertical MOS field effect transistor, the method comprising: forming a source region. 2. After the step of forming the high concentration region of one conductivity type,
2. The method of manufacturing a vertical MOS field effect transistor according to claim 1, further comprising the step of forming a high concentration region of an opposite conductivity type directly above the high concentration region.