JP5440169B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a manufacturing method thereof, and further relates to a semiconductor device having an impact ionization MISFET based on the principle of carrier avalanche multiplication by ionization collision , and a manufacturing method thereof .

  In recent years, impact ionization MISFETs have been proposed and studied. The impact ionization MISFET is a semiconductor element that uses the principle of avalanche multiplication of carriers (electrons and holes) by ionization collision (impact ionization), and has a characteristic that a flowing current increases rapidly when avalanche multiplication occurs. Utilizes the on-off characteristics of the device. The impact ionization MISFET can operate at high speed using a steep change in current during on-off, and is expected to be applied as a high-speed semiconductor switching element in place of the MISFET.

  Hereinafter, the structure and operating principle of a typical impact ionization MISFET will be described with reference to FIGS. 7A and 7B. 7A and 7B are schematic cross-sectional views of a planar-type impact ionization MISFET, and show an off state and an on state, respectively.

  7A and 7B, a drain region 103 composed of a high concentration n-type diffusion layer and a source region 104 composed of a high concentration p-type diffusion layer are formed on the surface region of the p-type silicon substrate 101 having a low impurity concentration. Is formed. A gate electrode 106 is formed on the p-type silicon substrate 101 via a gate oxide film 105. Although not shown, the semiconductor device includes other elements such as an element isolation region, an interlayer insulating film covering the whole, a gate electrode, an n-type drain region, and a wiring to the source region. The gate electrode 106 is formed at a position closer to the n-type drain region 103 than the p-type source region 104.

  In the off state of FIG. 7A, no channel is formed under the gate insulating film 105. When the drain-source potential difference (VDS) is increased under a voltage condition in which the drain voltage (VD) is higher than the source voltage (VS), most of the voltages are applied to the n-type drain region 103 and the p-type source region 104. To the p-type silicon substrate between. When VDS becomes sufficiently large, p-type silicon substrate 101 is completely depleted. In this state, the drain current becomes a reverse saturation current in the reverse bias state of the PIN junction, and therefore hardly flows.

  When the gate voltage (VG) is increased while the drain-source voltage VDS is maintained at a relatively high voltage, as shown in FIG. 7B, in the vicinity of the surface of the p-type silicon substrate 101 under the gate insulating film 105 Is inverted to n-type, and the channel 120 is formed. As a result, the effective width in the horizontal direction of the depletion layer formed in the p-type silicon substrate 101 is narrowed, so that the electric field strength in the depletion layer is increased, and the electrons 110 injected from the source region 104 into the depletion layer are generated. Generate impact ionization. Impact ionization is generated in a chain in the depletion layer by avalanche multiplication, and the drain current is rapidly increased.

  The drain-source voltage VDS is set to a voltage range in which impact ionization does not occur when the channel 120 is not formed and impact ionization occurs when the channel 120 is formed.

  In the present specification, the gate voltage necessary for forming the channel 120 is hereinafter referred to as a gate threshold voltage, and the drain-source voltage necessary for generating impact ionization in the state where the channel 120 is formed. VDS is called a drain threshold voltage. Further, of the surface region of the p-type silicon substrate 101 between the n-type drain region 103 and the p-type source region 104, a region where a channel is formed by an increase in gate voltage is a channel region, and a region where no channel is formed Is called the impact ionization region 121.

  The drain threshold voltage depends on the material and distance of the impact ionization region 121. As for the material, a material having a narrow band gap such as silicon germanium or germanium is preferable to silicon. This is because these materials have a higher impact ionization rate and a lower drain threshold voltage than silicon. Further, since the electric field becomes stronger as the distance of the impact ionization region 121 is shorter, the drain threshold voltage is smaller. For example, in order to set the drain threshold voltage to 1 V or less, germanium is used as the material, and the length of the impact ionization region 121 is set to 50 nm or less.

  In the impact ionization MISFET, the channel 120 is formed only in the vicinity of the surface of the channel region, as in a normal MOSFET. However, since the dominating power of the gate is weak between the channel 120 and the source 104, carriers are conducted while spreading from the channel 120 toward the source 104. The electrons 110 that conduct in the deep part of the p-type substrate 101 conduct toward the channel 120, and thus have a velocity component in the substrate depth direction (vertical direction) from the inside of the substrate toward the gate electrode.

  Impact ionization occurs not only in the surface region of the substrate but also in a deep region. As shown in the figure, high energy electrons generated in the deep region of the substrate have a velocity component in the substrate depth direction toward the gate electrode 106. For this reason, in the impact ionization MISFET, there is a problem that the probability that electrons are injected into the gate insulating film 105 is increased, and the reliability of the element is lowered due to characteristic fluctuations such as threshold current and on-current. As described above, in order to lower the drain threshold voltage, it is preferable to reduce the impact ionization region. When the source region has the same depth, the vertical component of the velocity vector of electrons flowing in the deep region becomes relatively large with miniaturization, and the increase in the proportion of electrons having the vertical component increases the reliability problem. To do.

An object of the present invention is to provide a semiconductor device having an impact ionization MISFET based on the principle of carrier avalanche multiplication by ionization collision , and a method for manufacturing the semiconductor device , and a semiconductor device having high reliability , and a method for manufacturing the semiconductor device . There is.

The present invention includes a gate insulating film formed on a surface of a semiconductor region composed of a first conductivity type or an intrinsic semiconductor,
A gate electrode formed on the gate insulating film; a second conductivity type high-concentration impurity region formed on the semiconductor region adjacent to one side surface of the gate electrode; and the other side surface of the gate electrode is formed spaced apart from on the semiconductor region and the interface between the semiconductor region, as viewed in the direction normal to the interface between the semiconductor region and the gate insulating film, the on state, the semiconductor under the gate electrode position equal or the peak position of carrier concentration in the region, or, have a, a high concentration impurity region of the first conductivity type at a position closer to the gate electrode than the peak position, the high concentration of the first conductivity type The interface between the impurity region and the semiconductor region and a part of the surface of the semiconductor region between the gate electrode and the high-concentration impurity region of the first conductivity type are the interface between the gate insulating film and the semiconductor region. Also provides a semiconductor device comprising a side near Rukoto closer to the gate electrode when viewed in the direction normal to the interface.

The present invention also includes a step of forming a gate insulating film and a gate electrode on the first conductivity type semiconductor region, and a second conductivity type at a position adjacent to one side surface of the gate electrode in the semiconductor region. forming a high concentration impurity region, on the surface of the semiconductor region, a step of selectively growing the high concentration impurity layer of the first conductivity type at a position away from the other side before Symbol gate electrode, by heat treatment, forming said first conductivity type high concentration impurity layer by diffusing impurities into the semiconductor region, the high concentration impurity region of a first conductivity type including a surface portion of said high concentration impurity layer and the semiconductor region, A method for manufacturing a semiconductor device is provided.

The present invention further includes a step of forming a first conductivity type diffusion region on a surface portion of a semiconductor substrate, and sequentially forming a first insulating film and a gate electrode on the surface of the first conductivity type diffusion region. a step of, depositing a second insulating film covering the gate electrode, the second insulating film, said gate electrode, and, by forming an opening through said first insulating film, the A step of exposing a diffusion region of the first conductivity type, a step of forming a gate insulating film on a side wall of the opening of the gate electrode, and a height of the first conductivity type partially overlapping the gate electrode in the opening. A step of sequentially depositing a concentration impurity layer and an intrinsic or lightly doped semiconductor layer; a step of removing a part of the second insulating film to expose a sidewall of the intrinsic or lightly doped semiconductor layer; and the gate the upper electrode and the second insulating film, the exposed An impurity is introduced into the intrinsic or low-doped semiconductor layer from the high-concentration impurity layer of the second conductivity type by a step of growing a high-concentration impurity layer of the second conductivity type surrounding the sidewall of the intrinsic or low-doped semiconductor layer and heat treatment. diffusion to, and having a step of forming a high-concentration impurity region of the second conductivity type which includes a surface portion of said high concentration impurity layer of the second conductivity type and the intrinsic or lightly doped semiconductor layer semiconductor An apparatus manufacturing method is provided.

  According to the present invention, it is possible to provide a semiconductor device having an impact ionization MISFET based on the principle of avalanche multiplication of carriers due to ionization collision and having improved reliability, and a method for manufacturing the same.

  The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the drawings.

It is sectional drawing which shows the impact ionization MISFET of the semiconductor device which concerns on 1st Embodiment of this invention. 2A to 2D are cross-sectional views sequentially showing manufacturing steps of the semiconductor device of FIG. It is sectional drawing which shows the impact ionization MISFET of the semiconductor device which concerns on 2nd Embodiment of this invention. 4A to 4E are cross-sectional views sequentially showing manufacturing steps of the semiconductor device of FIG. It is sectional drawing which shows the impact ionization MISFET of the semiconductor device which concerns on 3rd Embodiment of this invention. FIG. 6 is a cross-sectional view sequentially showing manufacturing steps of the semiconductor device of FIG. 5. 7A and 7B are cross-sectional views showing the off state and the on state of a conventional impact ionization MISFET, respectively.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected and shown to the same element. FIG. 1 is a cross-sectional view showing an impact ionization MISFET of the semiconductor device according to the first embodiment of the present invention. An n-type drain region 11 and a p-type source region 12 having an impurity concentration of 1 × 10 20 cm −3 or more are formed in and on the p-type silicon substrate 10 having a low impurity concentration. A gate insulating film 13 and a gate electrode 14 are formed on a part of the p-type silicon region 1 between the n-type drain region 11 and the p-type source region 12. An insulating film 15 whose opening defines the p-type source region 12 is formed. Although not shown in the figure, in the semiconductor device, an element isolation region such as a shallow trench for isolating the impact ionized MISFET from each other, a silicide layer on the source, drain and gate, and silicon oxide covering the whole Other elements such as an interlayer insulating film such as a film, and wiring for electrically connecting each impact ionization MISFET and other elements are formed.

  As shown in the figure, the position of the surface (bottom surface) of the p-type source region 12 in contact with the surface of the p-type silicon substrate 10 is inside the p-type silicon substrate 10. In the impact ionization MISFET, when a positive voltage equal to or higher than the threshold voltage is applied to the gate voltage to turn it on, a channel 20 is formed under the gate electrode. The depth direction distribution of the electron concentration inside the channel region has a concentration peak at a depth of 2 to 10 nm.

  The position of the interface between the p-type source region 12 and the p-type substrate 11 is the peak position of the distribution of the electron concentration in the channel 20 in the depth direction when viewed in the normal direction to the interface between the gate insulating film 13 and the p-type silicon substrate 10. It may be substantially equal to (peak depth) or on the side closer to the gate electrode 14 than the peak position. In other words, the position of the bottom surface of the p-type source region 12 is formed at the peak position of the distribution in the depth direction of the electron concentration in the channel region or at a position shallower than the peak position. With this configuration, carriers conducted between the channel region and the p-type source region 12 flow substantially along the surface of the p-type silicon substrate 10, and the carrier velocity vector is parallel to the surface of the p-type silicon region 1. is there. Therefore, impact ionization occurs near the surface, and the vector of impact ionization is parallel to the surface of the p-type silicon region 1. Since carriers with high energy do not have a velocity component in the thickness direction of the gate electrode 14, the probability of being injected into the gate insulating film 13 is reduced, and the reliability is improved.

  In the present embodiment, the bottom surface of the p-type source region 12 is formed inside the silicon substrate 10. The bottom surface is formed closer to the gate electrode than the interface between the gate insulating film and the semiconductor region when viewed in the normal direction to the interface, in other words, above the interface position between the gate insulating film 13 and the silicon substrate 10. May be. In this case, a region from the bottom surface of the p-type source region 12 to the interface between the gate insulating film 13 and the silicon substrate 10 is added to the resistance. However, the velocity vector of carriers conducted through the impact ionization region 21 is parallel to the surface of the p-type silicon region 1, and therefore, the probability of being injected into the gate insulating film 13 is low, and the reliability is improved. Is obtained.

  Furthermore, although the impact ionization region is formed of the silicon substrate 10, it may be formed of silicon germanium or germanium having a band gap smaller than that of silicon. Since silicon germanium and germanium have a higher impact ionization rate than silicon, the drain threshold voltage can be reduced. In this case, the p-type source region 12 can also be the same silicon germanium or germanium as the substrate. As will be described later, the p-type source region 12 is formed by an epitaxial growth method. It is preferable to perform epitaxial growth using the same material as the substrate, since defects such as dislocation do not occur.

  In this embodiment, the silicon substrate 10 is used as the substrate. However, the substrate may be an SOI (silicon on insulator) substrate in which an insulating film such as a silicon oxide film is formed under silicon, or silicon germanium. Alternatively, an SGOI (silicon-germanium on insulator) substrate or a GOI (germanium on insulator) substrate in which an insulating film such as a silicon oxide film is formed under germanium may be used.

  Further, in the present embodiment, the n-type impact ionization MISFET has been described. However, the present invention is not limited to the n-type, and can be applied to a p-type impact ionization MISFET. In this case, an n-type region is adopted as the substrate region, a p-type high concentration impurity region is adopted as the drain region, and an n-type high concentration impurity region is adopted as the source region.

  2A to 2D show an example of a manufacturing method of the impact ionization MISFET shown in FIG. After an insulating film such as a silicon oxide film and a polysilicon film are formed on the surface of the p-type silicon substrate 10 having an impurity concentration of 1 × 10 15 cm −3 or less, the photolithography technique and the etching technique generally used are used. Then, the gate insulating film 13 and the gate electrode 14 are formed (FIG. 2A). Next, as shown in FIG. 2B, a photoresist mask 50 is formed, and an n-type drain region 11 is formed by ion implantation of arsenic with an implantation energy of about 10 keV and a dose of 1 × 10 13 cm −2 or more. Next, the photoresist mask 50 is removed.

  Next, as shown in FIG. 2C, an insulating film such as a silicon oxide film is deposited, and an insulating film 15 is formed by a photolithography technique and an etching technique. Thereafter, after removing the photoresist mask 51, as shown in FIG. 2D, a silicon epitaxial layer doped with 1 × 10 20 cm −3 or more of boron is selectively grown to form a high concentration p-type region 41. Alternatively, the high-concentration p-type region 41 may be formed by selectively growing a non-doped silicon epitaxial layer and then ion-implanting boron. Thereafter, heat treatment is performed at 1000 ° C. for about 10 seconds. As a result, boron diffuses from the high-concentration p-type region 41 into the p-type silicon substrate 10, and the impact ionization MISFET shown in FIG. 1 is formed.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 3 is a cross-sectional view showing an impact ionization MISFET according to the second embodiment of the present invention. 3 is the same as that of the first embodiment except for the items described below, and detailed description thereof is omitted. Although illustration is omitted, in practice, a semiconductor device includes an element isolation region such as a shallow trench for isolating impact ionized MISFETs from each other, a silicide layer on the source, drain and gate, and silicon oxide covering the whole. Other elements such as an interlayer insulating film such as a film and wiring for electrically connecting each impact ionized MISFET and other elements are formed.

  In the impact ionization MISFET of this embodiment, not only the surface of the p-type source region 44 but also a part of the surface of the impact ionization region 21 between the channel region and the p-type source region 44 is formed on the gate insulating film 13 and the semiconductor region. It is formed on the side closer to the gate electrode as viewed in the normal direction to the interface, that is, on the upper side than the interface. As described in the first embodiment, the position of the bottom surface of the p-type source region 44 is equal to or higher than the peak depth of the electron concentration of the channel 20. A sidewall insulating film 16 such as a silicon oxide film is formed on the side surface of the gate electrode 14 in order to define the position of the impact ionization region that selectively grows upward. A silicon epitaxial layer is formed in a region where the silicon substrate 10 is exposed on the surface other than the gate electrode 14 and the sidewall insulating film 16.

  As shown in the figure, a p-type source region 44 is formed above the channel 20, and a p-type silicon region connected to the p-type source region 44 is formed above the channel 20. For this reason, the direction of electrons from the p-type source region 44 toward the channel region changes from horizontal to downward. Therefore, the probability that high energy electrons generated by impact ionization are injected into the gate insulating film 13 is further reduced as compared with the first embodiment, and the reliability is further improved.

  In the present embodiment, the bottom surface of the p-type source region 44 is formed inside the silicon substrate 10, but the gate is viewed from the bottom surface in the direction normal to the interface rather than the interface between the gate insulating film 13 and the semiconductor region. It may be formed on the side close to the electrode, in other words, above the interface position between the gate insulating film 13 and the silicon substrate 10. Even in this case, the velocity vector of carriers conducted through the impact ionization region 21 is parallel or downward with respect to the surface of the p-type silicon region 1, and the probability of being injected into the gate insulating film 13 is low, and the reliability is improved. The effects of the invention can be obtained.

  Although the impact ionization region is formed of silicon, it may be formed of silicon germanium or germanium having a band gap smaller than that of silicon. As will be described later, a region formed above the channel region in the impact ionization region between the channel and the source is formed by epitaxial growth. In this epitaxial growth, silicon germanium or germanium may be grown instead of silicon. Since silicon germanium and germanium have a higher impact ionization rate than silicon, the drain threshold voltage can be reduced. In this case, the substrate can be the same silicon germanium or germanium as the epitaxial layer. Epitaxial growth of the same material as that of the substrate is preferable because no defect formation such as dislocation occurs.

  In the present embodiment, the silicon substrate 10 is used as the substrate. However, an SO substrate in which an insulating film such as a silicon oxide film is formed under silicon may be used instead of the silicon substrate. Alternatively, an SGOI substrate or a GOI substrate in which an insulating film such as a silicon oxide film is formed under silicon germanium or germanium may be employed.

  In the present embodiment, the n-type impact ionization MISFET has been described. However, the present invention is not limited to the n-type, and can be applied to a p-type impact ionization MISFET.

  4A to 4E show an example of a manufacturing method of the impact ionization MISFET shown in FIG. In a process similar to that described with reference to FIGS. 2A and 2B, as shown in FIG. 4A, a gate insulating film 13 and a p-type silicon substrate 10 having an impurity concentration of 1 × 10 15 cm −3 or less are formed on the surface. Gate electrode 14 and high concentration n-type region 31 are formed. Next, an insulating film such as a silicon oxide film is formed on the entire surface of the wafer and etched back to form a sidewall insulating film 16 as shown in FIG. 4B. As shown in FIG. 4C, a non-doped silicon layer 17 having a thickness of 50 to 100 nm is selectively epitaxially grown on a portion where the silicon substrate 10 is exposed on the surface other than the gate electrode 14 and the sidewall insulating film 16. Next, as shown in FIG. 4D, after a photoresist mask 52 is formed, arsenic is ion-implanted to form a high concentration n-type region 32. At this time, the upper high-concentration n-type region 32 is electrically connected to the lower high-concentration n-type region 31, and finally works as an n-type drain region 33.

  Next, after removing the photoresist mask 52, a photoresist mask 53 is formed, and boron is ion-implanted to form the high concentration p-type region. Thereafter, the photoresist mask 53 is removed, and heat treatment is performed at 1000 ° C. for about 10 seconds in order to activate the implanted impurities. As a result, boron diffuses from the high-concentration p-type region 42 into the p-type silicon substrate 10, and the impact ionization MISFET shown in FIG. 3 is formed.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 5 is a cross-sectional view showing an impact ionization MISFET according to the third embodiment of the present invention. Unlike the planar type in the first and second embodiments shown in FIGS. 1 and 3, the impact ionization MISFET of this embodiment constitutes a vertical MISFET. A high concentration n-type region 34 having an arsenic concentration of 1 × 10 19 cm −3 or more is formed in a p-type silicon substrate 10 having a low impurity concentration. An n-type drain region 35 having a phosphorus concentration of 1 × 10 20 cm −3 or more and a non-doped silicon epitaxial layer 91 are sequentially deposited so as to be connected to the high-concentration n-type region 34. Further, a p-type source region 47 having a boron concentration of 1 × 10 20 cm −3 or more is formed around the upper portion of the non-doped epitaxial layer. Further, a gate insulating film 51 and a gate electrode 61 are formed on the side surfaces of the n-type drain region 35 and the non-doped epitaxial layer. Further, insulating films 71 and 72 for electrically insulating the silicon substrate 10, the gate electrode 61, and the p-type source region 47 are formed. Although illustration is omitted, in practice, an element isolation region such as a shallow trench for isolating each impact ionized MISFET semiconductor device, a silicide layer on the source, drain and gate, a silicon oxide film covering the whole, etc. Other elements such as wiring for electrically connecting the interlayer insulating film and each impact ionized MISFET and other elements are formed. Instead of the non-doped silicon epitaxial layer 91, a low-doped silicon epitaxial layer may be deposited.

  The first and second embodiments shown in FIGS. 1 and 3 are planar MISFETs, in which the position of the impact ionization region 21 depends on the alignment accuracy of photolithography. As described above, the shorter the impact ionization region, the lower the drain threshold voltage, which is preferable. However, along with miniaturization, an expensive equipment investment is required for a photolithography apparatus such as an exposure apparatus. There's a problem. On the other hand, the MISFET of this embodiment is a vertical type, and the impact ionization region 21 can be controlled by the film thickness of the insulating film 72. For this reason, at least the formation of the impact ionization region 21 does not require an expensive photolithography apparatus or exposure mask. Therefore, the cost can be reduced, and the manufacturing can be performed only by controlling the film thickness.

  As shown, a p-type source region 47 is formed on the side surface of the non-doped epitaxial layer 91. Accordingly, carriers conducted between the channel region 22 and the source flow almost on the side surfaces. That is, the carrier velocity vector is parallel to the side surface of the non-doped epitaxial layer 91. Impact ionization also occurs near the side surface, and its vector is parallel to the side surface of the non-doped epitaxial layer 91. Since carriers with high energy do not have a velocity component in the thickness direction of the gate electrode 61, the probability of being injected into the gate insulating film 51 is reduced, and reliability is improved. The position of the bottom surface of the p-type source region 47 is the same as that described in the first embodiment, and the description thereof is omitted.

  In the present embodiment, the impact ionization region is formed by the non-doped silicon epitaxial layer 91. However, the impact ionization region may be formed of silicon germanium or germanium having a band gap smaller than that of silicon. Since silicon germanium and germanium have a higher impact ionization rate than silicon, the drain threshold voltage can be reduced. In this case, the n-type drain region 35 and the substrate 10 can also be made of silicon germanium or germanium.

  In the present embodiment, the substrate is the silicon substrate 10, but the substrate may be an SOI substrate in which an insulating film such as a silicon oxide film is formed under silicon. Alternatively, the substrate may be an SGOI substrate or an GOI substrate in which an insulating film such as a silicon oxide film is formed under silicon germanium or germanium.

  In the present embodiment, the n-type impact ionization MISFET has been described. However, the present invention is not limited to the n-type, and can be applied to a p-type impact ionization MISFET.

  Next, an example of a manufacturing method of the impact ionization MISFET shown in FIG. 5 is shown in FIGS. As shown in FIG. 6A, a high concentration n of 1 × 10 19 cm −3 or more is formed on the surface of a p-type silicon substrate 10 of 1 × 10 15 cm −3 or less by a commonly used photolithography technique and ion implantation technique. After the mold region 34 is formed, an insulating film 71 such as a silicon oxide film is formed. Next, after forming a polysilicon film doped with phosphorus by 1 × 10 20 cm −3 or more, the gate electrode 61 is formed by photolithography technique and etching technique. Next, as shown in FIG. 6B, after forming an insulating film made of a silicon nitride film 72 or a silicon oxide film 73, a region 90 where selective epitaxial growth is performed is formed by using a photolithography technique and an etching technique to form a high-concentration n-type region 34. Open until exposed.

  Next, as illustrated in FIG. 6C, the gate insulating film 51 is formed by oxidizing the gate electrode 61. Next, a silicon epitaxial layer doped with 1 × 10 20 cm −3 or more of phosphorus is selectively grown to form an n-type drain region 35, and then a non-doped silicon epitaxial layer 91 is selectively grown. Next, after removing the silicon oxide film 73, a high-concentration p-type polysilicon layer 46 doped with 1 × 10 20 cm −3 or more of boron is formed. Next, after applying a photoresist, etching back is performed to expose the surface of the high-concentration p-type polysilicon layer 46, and then a photoresist mask 53 is formed by a photolithography technique.

  Next, as shown in FIG. 6F, after the high-concentration p-type polysilicon layer 46 is etched, a heat treatment is performed at 1000 ° C. for about 10 seconds in order to activate the ion-implanted impurities. Thereby, boron diffuses from the high-concentration p-type polysilicon layer 46 into the silicon epitaxial layer 91, and the impact ionized MISFET shown in FIG. 5 is formed.

  The n-type drain region 35 and the non-doped epitaxial layer 91 formed by epitaxial growth preferably employ epitaxial growth of the same material as the substrate. Epitaxial growth of the same material prevents the formation of defects such as dislocations.

  Although the invention has been particularly shown and described with reference to illustrative embodiments, the invention is not limited to these embodiments and variations thereof. It will be apparent to those skilled in the art that various modifications can be made to the present invention without departing from the spirit and scope of the invention as defined in the appended claims.

  This application is based on and claims the priority of Japanese Patent Application No. 2007-209326 filed on Aug. 10, 2007, the entire contents of which are incorporated herein by reference. join.

Claims (8)

A gate insulating film formed on a surface of a semiconductor region composed of a first conductivity type or an intrinsic semiconductor;
A gate electrode formed on the gate insulating film;
A second conductivity type high-concentration impurity region formed on the semiconductor region adjacent to one side surface of the gate electrode;
Formed on the semiconductor region spaced apart from the other side surface of the gate electrode, and the interface with the semiconductor region is in the normal direction with respect to the interface between the gate insulating film and the semiconductor region. A high-concentration impurity region of a first conductivity type at a position equal to the peak position of the carrier concentration in the semiconductor region under the gate electrode or a position closer to the gate electrode than the peak position;
The interface between the high-concentration impurity region of the first conductivity type and the semiconductor region, and a part of the surface of the semiconductor region between the gate electrode and the high-concentration impurity region of the first conductivity type are the gate insulation. A semiconductor device, wherein the semiconductor device is closer to the gate electrode than the interface between the film and the semiconductor region in the normal direction to the interface.   The semiconductor device according to claim 1, wherein the high-concentration impurity region of the first conductivity type is formed by selective epitaxial growth and subsequent heat treatment.   The part of the semiconductor region between the gate electrode and the high-concentration impurity region of the first conductivity type and the high-concentration impurity region of the first conductivity type are formed by selective epitaxial growth. Item 14. The semiconductor device according to Item 1.   4. The device according to claim 1, wherein at least one of the semiconductor region and the high-concentration impurity region of the first conductivity type is formed of silicon, silicon germanium, or germanium. 5. Semiconductor device.   The semiconductor device according to claim 1, wherein an insulating film is formed below the semiconductor region. Forming a gate insulating film and a gate electrode on the semiconductor region of the first conductivity type;
Forming a second conductivity type high concentration impurity region at a position adjacent to one side surface of the gate electrode of the semiconductor region;
Selectively growing a high-concentration impurity layer of the first conductivity type on the surface of the semiconductor region at a position away from the other side surface of the gate electrode;
By heat treatment, impurities are diffused from the first conductivity type high concentration impurity layer into the semiconductor region to form a first conductivity type high concentration impurity region including the high concentration impurity layer and a surface portion of the semiconductor region. And a method of manufacturing a semiconductor device. Prior to the step of selectively growing the high concentration impurity layer of the first conductivity type, selectively forming an insulating film adjacent to the side surface of both of the gate electrode, spaced apart from the other side surface of said gate electrode A step of selectively removing the insulating film at the position and forming a removal region. In the selective growth step, the high-concentration impurity layer of the first conductivity type is selectively formed in the removal region. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is deposited. Forming a diffusion region of the first conductivity type on the surface portion of the semiconductor substrate;
Sequentially forming a first insulating film and a gate electrode on the surface of the diffusion region of the first conductivity type;
Depositing a second insulating film over the gate electrode;
Forming an opening penetrating the second insulating film, the gate electrode, and the first insulating film to expose the diffusion region of the first conductivity type;
Forming a gate insulating film on the sidewall of the opening of the gate electrode;
Sequentially depositing a first conductivity type high concentration impurity layer partially overlapping with the gate electrode and an intrinsic or lightly doped semiconductor layer in the opening;
Removing a portion of the second insulating film to expose a side wall of the intrinsic or lightly doped semiconductor layer;
Growing a second conductivity type high-concentration impurity layer surrounding the exposed intrinsic or low-doped semiconductor layer on the gate electrode and the second insulating film;
By heat treatment, impurities are diffused from the second conductivity type high-concentration impurity layer into the intrinsic or low-doped semiconductor layer, and surface portions of the second conductivity type high-concentration impurity layer and the intrinsic or low-doped semiconductor layer are formed. And a step of forming a high-concentration impurity region of the second conductivity type including the semiconductor device manufacturing method.

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