JP2002110971A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem, where at the time of breakdown, impact ionization occurs many times immediately under a gate electrode and the operation characteristics of a semiconductor device change. SOLUTION: Since the impurity of an off-set layer 5 is introduced to a position deeper than the position where the concentration of an impurity introduced to a p-well layer 2 reaches its peak, a p-n junction face is formed at a region where the concentration of a p-type impurity is high. Since the impact ionization occurs many times immediately below an n+-type diffusion layer 6 separated from the gate electrode 3, the injection of hot electrons into a gate-insulating film can be prevented. Consequently, variations in the characteristics of a MOSFET caused by the fluctuation of its threshold voltage can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, a semiconductor device, and more particularly, to a power MOSFET.

[0002]

2. Description of the Related Art Conventionally, there has been known a power IC in which a power semiconductor element used for a drive circuit and the like and a low voltage semiconductor element used for a low withstand voltage control circuit and the like are formed on the same circuit board. A power MOSFET used in the output stage of this type of power IC generally requires a higher breakdown voltage and a lower on-resistance than the control unit described above.

FIG. 4 shows an example of a conventional power MOSFET. In FIG. 4, the p-type semiconductor substrate
The p ⁺ -type diffusion layer 23 and the n ⁺ -type diffusion layer 2 are formed in the well layer 22.
4 are formed, and a source electrode 25 is provided thereon. Further, a drain electrode 28 is provided on the n ⁺ type diffusion layer 27 formed in the n drift layer 26. In addition, LOCOS (Local O
xidation of silicon) oxide film 30
Is formed, the electric field in this portion is reduced.

[0004]

However, in the power MOSFET having the above structure, the breakdown voltage is determined by the width of the LOCOS oxide film 30. For this reason, it is difficult to miniaturize the element with a low withstand voltage.

[0005] In spite of being a low withstand voltage element, n
Since the width of the drift layer 26 cannot be reduced, there is a problem that the on-resistance increases.

FIG. 5 shows another conventional example. This power MOSFET is, as shown in FIG.
1 has a P-well layer 32 provided therein. A gate electrode 33 is provided on the p-well layer 32 via a gate insulating film. In the p-well layer 32 located on both sides of the gate electrode 33, an n ⁺ type diffusion layer 34 as a source is provided.
And an offset layer 35 composed of an n ⁻ type diffusion layer. In the offset layer 35, n as a drain
^{A +} type diffusion layer 36 is provided. Further, the p ⁺ -type diffusion layer 3 is in contact with the n ⁺ -type diffusion layer 34 in the p-well layer 32.
7 are formed. A source electrode 38 is formed on the p ⁺ type diffusion layer 37 and the n ⁺ type diffusion layer 34, and a drain electrode 39 is formed on the n ⁺ type diffusion layer 36. Incidentally, 40
Is an insulating film.

According to the above configuration, the electric field at the interface between the p-type region and the n-type region can be weakened by the offset layer 35, and a high breakdown voltage and a low on-resistance can be realized. Moreover, unlike the configuration shown in FIG.
Miniaturization is possible.

FIG. 6 shows an impurity concentration profile in the depth direction along 5A-5A in FIG. As shown in FIG. 5, the depth of the offset layer 35 is n
It is formed slightly deeper than the ⁺ type diffusion layer 36. Therefore, an n ⁻ -type impurity is introduced into a region shallower than the peak position of the p-type impurity concentration shown in FIG. 6, and a pn junction having a p-type impurity concentration of about 1.1 × 10 ¹⁷ atm / cm ³ in this shallow region. Are formed. Therefore, when a high voltage is applied, the depletion layer spreads in the depth direction, and the electric field in the depth direction does not increase.

FIG. 7 shows the distribution of the impact ionization rate when the gate electrode 33 and the source electrode 38 are grounded and a high voltage is applied to the drain electrode 39 to cause a breakdown. Reference numeral 41 in FIG. 7 denotes a depleted layer region. In FIG. 7, a to d indicate the number of impact ionization occurrences per cubic centimeter per second.
As shown in FIG. 7, when the depth of the offset layer 35 is shallower than the peak position of the impurity concentration of the p-well layer 32, an electric field concentrates directly below the gate electrode 33, and impact ionization occurs frequently in this portion. When impact ionization occurs, hot electrons are generated. The hot electrons enter the gate electrode 33 and change the threshold voltage. Therefore, there is a problem that the operating characteristics of the MOSFET change.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce the impact ionization rate immediately below a gate and prevent a change in operating characteristics due to hot electrons. It is an object of the present invention to provide a semiconductor device.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
In order to solve the above problems, a first conductivity type well layer formed on a semiconductor substrate, a gate electrode formed on the well layer via a gate insulating film, and a gate electrode on one surface side of the gate electrode A second conductivity type source diffusion layer selectively formed in the well layer; a second conductivity type offset layer formed in the well layer on the other surface side of the gate electrode;
In the semiconductor device having the second conductivity type drain diffusion layer formed in the offset layer, the impurity of the offset layer is formed to a position deeper than a peak position of the impurity concentration of the well layer. And

Further, the semiconductor device is characterized in that when a voltage is applied between the source diffusion layer and the drain diffusion layer, breakdown occurs immediately below the diffusion layer.

The semiconductor device is characterized in that the well layer has an impurity concentration of 2 × 10 ^{17 to} 3 × 10 ¹⁷ atm / cm ³ at a junction surface between the offset layer and the well layer.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a power MOSFET according to the present invention.
It is sectional drawing which shows schematically. As shown in FIG.
A p-well layer 2 is provided in a substrate 1. This p-we
A gate electrode 3 is provided on the gate layer 2 via a gate insulating film.
Have been killed. The p-wells located on both sides of the gate electrode 3
N in the well layer 2 as a source⁺Type diffusion layer 4 and n ^―
An offset layer 5 composed of a mold diffusion layer is provided. This
N as a drain in the offset layer 5 of FIG.⁺Diffusion layer 6
Is provided. Further, in the p-well layer 2, n⁺
In contact with the mold diffusion layer 4⁺A mold diffusion layer 7 is formed.
This p⁺Diffusion layer 7 and n⁺Source electrode 8 on type diffusion layer 4
Are formed, and n⁺Electrode 9 is formed on the diffusion layer 6
Have been. Reference numeral 10 denotes an insulating film.

The offset layer 5 is formed deeper than the n ⁺ type diffusion layer 6, and the junction surface between the offset layer 5 and the p well layer 2 is formed at a position deeper than the conventional one from the surface of the p well layer 2. Have been.

FIG. 2 shows an example of an impurity profile in a depth direction of a cross section taken along line 1A-1A in FIG. As described above, the power MOSFET of the present invention
The offset layer 5 is formed deep. Therefore, as shown in FIG. 2, the n ⁻ -type impurity in the offset layer 5 is introduced deeper than the peak position of the p-type impurity concentration in the p-well layer 2, and the p-type impurity is introduced into a region where the n ⁻ -type impurity concentration is high. The peak of the impurity concentration is located. That is, a pn junction is formed in a region having a high n ⁻ -type impurity concentration. The p-type impurity concentration in this region is 2.5 × 10 ¹⁷ atm / cm ³
When a high voltage is applied, the electric field is maximized in this region, and breakdown occurs. The doping concentration in FIG. 2 indicates the total concentration of the implanted impurities.

FIG. 3 schematically shows the impact ionization rate at the time of breakdown of the power MOSFET according to the present invention. In FIG. 3, reference numeral 11 denotes a depleted region. In the case of the present invention, a maximum electric field is generated immediately below the n ⁺ type diffusion layer 6. For this reason, as shown in FIG. 3, impact ionization frequently occurs immediately below the n ⁺ type diffusion layer 6. This position is apart from the gate electrode 3. Therefore, it is possible to prevent hot electrons generated by impact ionization from being injected into the gate insulating film.

According to the above configuration, n ⁻
Since the p-type impurity is introduced deeper than the peak position of the p-type impurity in the p-well layer 2, a pn junction surface can be formed at a point where the n ⁻ -type impurity concentration and the p-type impurity concentration are high. For this reason, the electric field is maximized immediately below the n ⁺ -type diffusion layer 6 near the junction surface, and impact ionization frequently occurs in this portion. Therefore, as compared with the related art, hot electrons are generated at a position far from the gate electrode 3, so that injection of the hot electrons into the gate insulating film can be prevented, and fluctuation of the threshold voltage can be prevented. Therefore, a change in the operation characteristics of the power MOSFET can be reduced.

Of course, various modifications can be made without departing from the scope of the present invention.

[0021]

As described in detail above, according to the present invention,
A semiconductor device can be provided which can reduce the impact ionization rate immediately below the gate and can prevent a change in operating characteristics due to hot electrons.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a power MOSFET according to the present invention.

FIG. 2 is a diagram showing an impurity profile in a depth direction of a power MOSFET according to the present invention.

FIG. 3 is a diagram showing an impact ionization rate of the power MOSFET according to the present invention.

FIG. 4 is a sectional view showing a conventional example of a power MOSFET.

FIG. 5 is a sectional view showing a conventional power MOSFET.

FIG. 6 is a diagram showing an impurity profile in a depth direction of a conventional power MOSFET.

FIG. 7 is a diagram showing an impact ionization rate of a conventional power MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... P well layer, 3 ... Gate electrode, 4 ... N ⁺ type diffusion layer, 5 ... Offset layer, 6 ... N ⁺ type diffusion layer, 7 ... P ⁺ type diffusion layer, 8 ... Source electrode, 9: drain electrode, 10: insulating film.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akio Nakagawa 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba R & D Center (reference) 5F040 DA06 DA20 DA22 DC01 EB01 EB02 EF01 EF11 EF18 EM02 EM03

Claims (3)

[Claims] A first conductivity type well layer formed on a semiconductor substrate; a gate electrode formed on the well layer via a gate insulating film; and the well layer on one surface side of the gate electrode A second conductivity type source diffusion layer selectively formed therein, a second conductivity type offset layer formed in the well layer on the other surface side of the gate electrode, and a second conductivity type offset layer formed in the offset layer. A semiconductor device having the second conductivity type drain diffusion layer, wherein the impurity of the offset layer is formed to a position deeper than a peak position of the impurity concentration of the well layer. 2. The semiconductor device according to claim 1, wherein when a voltage is applied between the source diffusion layer and the drain diffusion layer, breakdown occurs immediately below the drain diffusion layer. 3. An impurity concentration of the well layer at a junction surface between the offset layer and the well layer is 2 × 10 ¹⁷ to 3.
2. The semiconductor device according to claim 1, wherein the density is 3 × 10 ¹⁷ atm / cm ³ .