JPH04245480A - Mos type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the transconductance gm value of the title MOS type semiconductor device while providing the element structure having enhanced hot electron resistance on the drain side in relation to the channel MOS semiconductor device and manufacture thereof. CONSTITUTION:The title MOS type semiconductor device is composed of a one conductivity type semiconductor substrate 1, a source region 10 formed by depositing an inverse conductivity type semiconducty type semiconductor layer to that of said semiconductor substrate 1 as if buried in a recess formed by anisotropically etching away the substrate 1, a drain region 11 formed by depositing said inverse conductivity type semiconductor layer up to the position higher than the channel surface of said semiconductor substrate and a gate electrode 7 formed between said source region 10 and said drain region 11 through the intermediary of an insulating film.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a MOS type semiconductor device,
In particular, so-called short channel MO with short channel length
The present invention relates to an S transistor and its manufacturing method.

0002

[Prior art] In recent years, with the advancement of microfabrication technology,
The gate length of MOS transistors ranges from submicron to 0.
．． It is reaching the deep submicron level of 3 μm or less, and prototypes of devices with a diameter of 0.1 μm or less have been reported at the research level.

In such a device, the dimensions of the channel, which is the active region of the device, are close to the mean free path of carriers in the device, so the transport state of carriers emitted at high speed from the source region is microscopically The state becomes unsteady, and the relaxation times of energy and momentum do not match, resulting in so-called velocity overshoot, in which carriers travel faster than expected from the energy value, and carriers reach the source region without colliding with each other. Effects such as ballistic transport that travels from the to the drain region appear. As a result, a favorable effect is brought about in that the transconductance (gm) increases more than predicted from the conventionally known scaling law (proportional reduction law).

FIG. 3 is an explanatory diagram of the structure of a conventional short channel MOS transistor. In this figure, 31
3 is a p-type silicon substrate, 32 is a field oxide film, and 3 is a p-type silicon substrate.
3 is a gate insulating film, 34 is a polysilicon layer, 35 is a silicide layer, 36 is a gate electrode, 37 is an oxide film, 38 is an n
+ type source region, 39 is n + type drain region, 40
41 is a side wall, 41 is a source electrode, and 42 is a drain electrode.

This MOS transistor has a field oxide film 32 formed around the element formation region of a p-type silicon substrate 31, a gate insulating film 33 formed on the upper surface, and a polysilicon layer 34 and a silicide layer 35 formed thereon. After forming an oxide film 37, etching away the portions of these layers or films 34, 35, and 37 other than the gate region, and forming a gate electrode 36 using the remaining polysilicon layer 34 and silicide layer 35, type impurity is ion-implanted to form n+
After forming a type source region 38 and an n+ type drain region 39 and forming a sidewall 40 around the gate electrode 36, a source electrode 41 and a drain electrode 4 are formed in the n+ type source region 38 and the n+ type drain region 39, respectively.
2.

As described above, in the conventional deep submicron MOS transistor, both the source region 38 and the drain region 39 are formed by impurity ion implantation, which increases the potential gradient at the boundary between the source region and the channel. Therefore, in order to promote unsteady transport of carriers, it has been considered to make the impurity profile of the source region as steep as possible. For example, in the manufacturing process of the above-mentioned deep submicron MOS transistor, in order to suppress thermal diffusion of the impurity implanted into the source region, in the case of an n-channel MOS, the impurity is antimony, which is a heavy element with a small diffusion coefficient. or use
RTA (R
An attempt was made to minimize thermal diffusion of impurities by using a rapid thermal annealing method.

[0007]

[Problem to be Solved by the Invention] However, since the source region is basically formed by ion implantation, there is a limit to obtaining a steep impurity profile even with the above-mentioned measures. . On the other hand, regarding the drain side, when operating without lowering the power supply voltage too much, if electric field concentration occurs in this region, a so-called hot carrier effect will occur due to impact ionization.
In order to suppress this phenomenon, some kind of device is required to alleviate the concentration of the electric field. Therefore, depending on the conventional manufacturing method, MO
It was not possible to take full advantage of the advantages of the S-type transistor. In view of the above points, it is an object of the present invention to provide an element structure in which the transconductance gm of a MOS transistor with a deep submicron gate length is increased to a higher value, and the hot carrier resistance on the drain side is also improved. shall be.

[0008]

[Means for Solving the Problems] A MOS type semiconductor device according to the present invention includes a semiconductor substrate of one conductivity type, and a semiconductor substrate that is opposite to the semiconductor substrate so as to fill a recess formed by anisotropically etching away the semiconductor substrate. A source region formed by growing a semiconductor layer of a conductivity type, a drain region formed by growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate to a position higher than the channel surface of the semiconductor substrate, and the source region. and a gate electrode formed with an insulating film interposed between the drain region and the drain region.

Further, in the method for manufacturing a MOS type semiconductor device according to the present invention, at least a portion of the semiconductor substrate corresponding to a source region is anisotropically formed using a gate electrode formed on a semiconductor substrate of one conductivity type as a mask. a step of etching away the semiconductor substrate; and a step of filling the recess removed by the step and simultaneously growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate in a portion corresponding to the drain region to a position higher than the channel surface. A process was adopted in which a source electrode was formed in a semiconductor layer grown in a portion corresponding to a source region, and a drain electrode was formed in a semiconductor layer grown in a portion corresponding to a drain region.

0010

[Operation] In the present invention, the source region is formed by growing a semiconductor layer by low-temperature vapor phase growth in a recess with vertical walls that has been removed by anisotropic etching. Since the end of the region can be formed almost perpendicularly to the channel and in the form of a stepped junction, carrier injection can be made efficient and unsteady transport typified by velocity overshoot can easily occur. As a result, compared to devices formed by conventional ion implantation, the gm
has a larger value. In addition, since the drain region has a so-called stacked drain structure in which it is raised to a higher level than the plane of the channel region, a high impurity concentration region is not formed under the gate electrode, and therefore, electric field concentration near the drain is avoided. This suppresses the generation of hot carriers.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. (First Example) (MOS Type Semiconductor Device) FIG. 1 is a sectional view of a MOS type semiconductor device which is an example of the present invention. In this figure, 1 is a p- type silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is an n+ type polysilicon layer, 5 is a W or Ti silicide layer, 6 is an oxide film, 7 is a gate electrode, 8 is a protective film, 10 is an n+ type source region, 11 is an n+ type drain region, 12 is a side wall, and 13 and 14 are silicide layers.

This device includes an isolation field oxide film 2 formed around an element formation region of a p-type silicon substrate 1, and a region within the field oxide film 2 via a gate oxide film 3. A gate electrode 7 made of an n+ polysilicon layer 4 and a W or Ti silicide layer 5 formed thereon as necessary, and at least the silicon substrate 1 in the source region are anisotropically etched to a depth of 50 to 100 nm. a single-crystal or polycrystalline n+ type source region 10 formed so as to fill a recess of about 100 yen, and a single-crystalline or polycrystalline n+ type drain region 1 formed to be higher than the surface of the silicon substrate 1.
1.

Note that the illustrated oxide film 6 and protective film 8 are films that protect the silicide layer 5 or polysilicon layer 4 constituting the gate electrode 7, and the sidewalls 12 of the side walls of the gate electrode 7 are It is formed to ensure insulation between the silicide layer 13 on the side and the gate electrode 7 and between the gate electrode 7 and the silicide layer 14 on the drain side. Further, silicide layers 13 and 14 are formed on the source region and the drain region in order to lower the contact resistance between the source electrode and the drain electrode.

According to the device of this embodiment, the end of the source region is almost perpendicular to the channel and has a stepped junction shape, so carrier injection is efficient and unsteady transport such as velocity overshoot is effectively caused. be able to. As a result, gm can be made larger than in devices formed by conventional ion implantation. Further, since the drain region has a stacked structure raised higher than the plane of the channel region, concentration of electric field near the drain can be avoided and generation of hot carriers can be suppressed.

(Second Embodiment) (Method of Manufacturing a MOS Type Semiconductor Device) FIG. 2 is a manufacturing process diagram of an embodiment of the method of manufacturing a MOS type semiconductor device of the present invention. In this figure, 9
The structure is the same as that described with the same reference numerals in FIG. 1, except that 10a is a resist pattern and 10a is a depression in the source region. Hereinafter, the manufacturing process of an embodiment of the present invention will be described with reference to FIG. 2 for an n-chMOS.

I. (See FIG. 2A) First, an isolation field oxide film 2 is formed around the element formation region of the p- type silicon substrate 1 by a conventional process. Next, a gate oxide film 3 is formed by thermal oxidation, an n+ type polysilicon layer 4 is formed thereon by CVD, a W or Ti silicide layer 5 is formed thereon as needed, and silicon oxide is formed on top of the n+ type polysilicon layer 4. Grow layer 6. Next, these layers are selectively removed by lithography and etching techniques, and a gate electrode 7 is formed from the n+ type polysilicon layer 4 and the W or Ti silicide layer 5. In addition, the gate length is 0.25
It is in the range of ~0.1 μm. Then, the side portions of the gate electrode are lightly oxidized to form a protective film 8.

II. (See FIG. 2B) Thereafter, the oxide film 3 in the drain electrode region is selectively removed using a resist as a mask. Subsequently, another resist pattern 9 is used to cover the drain region and expose the source region.
Using the resist pattern 9, the gate electrode 7 or its surrounding insulating films 6 and 8, and the field oxide film 2 as masks, the silicon substrate at least in the source region is exposed to CF4+.
Recess 1 was removed by anisotropic etching using H2.
Form 0a. The depth of the silicon substrate 1 to be removed at this time is approximately 50 to 100 nm.

III. (See FIG. 2(C)) After removing the resist pattern 9, the recess 10a of the source region etched in the previous step is filled, and at the same time, n-type doping is applied onto the drain region so as to be higher than the surface of the silicon substrate 1. The silicon layers 10 and 11 thus formed are selectively grown by low-temperature CVD. The silicon grown at this time may be polycrystalline or single crystalline, but CVD growth is preferably performed at as low a temperature as possible so that n-type impurities do not auto-dope into the channel region during growth. This kind of CVD
The growth is carried out using, for example, Si2H6 at 10-3T.
orr, preferably an ultra-low pressure of about 10-8 Torr, 6
This can be achieved by a low-temperature process of about 00 to 800°C or a photoreaction CVD technique using UV irradiation. In this step, as described above, the n-type doped silicon layer may be selectively grown in the source region and the drain region, or it may be grown over the entire surface and then the n-type doped silicon layer may be grown in the source region, the drain region, and the Depending on the situation, a step may be taken to remove parts other than the extraction electrode by etching.

IV. (See FIG. 2(D)) Finally, if necessary, to ensure insulation between the source-side silicide layer 13 and the gate electrode 7 and between the gate electrode 7 and the drain-side silicide layer 14, which will be formed later. For example, a sidewall 12 is formed on the sidewall of the gate electrode 7 by a sidewall forming technique such as forming a SiO2 film on the entire upper surface by CVD and anisotropic etching.
Thereafter, silicide layers 13 and 14 are formed on the source region 10 and drain region 11 in order to lower the contact resistance between the source electrode and the drain. Note that the sidewalls 14 and 15 may not be necessary depending on the structure of the device and the manufacturing method.

According to the method of manufacturing a MOS type semiconductor device of this embodiment, a source structure having an impurity profile almost perpendicular to the channel and in the form of a stepped junction, and a stack raised to a higher position than the plane of the channel region. A type-drain structure can be realized by one-time crystal growth, and as a result, carrier injection in the source region becomes efficient, making unsteady transport such as velocity overshoot more likely to occur.
gm can be made to a large value, electric field concentration near the drain electrode can be avoided, and the generation of hot carriers can be suppressed. In the above embodiment, n-ch
Although the explanation was given using the example of a MOS transistor, p-ch
It goes without saying that even a MOS transistor can be realized by applying a similar process to a semiconductor of the opposite conductivity type.

[0021]

[Effects of the Invention] As explained above, according to the present invention, by using anisotropic etching and low temperature vapor phase growth,
It is possible to form a source region with steep impurity concentration and perpendicular to the channel, compared to MOS semiconductor devices in which source electrodes are formed using conventional ion implantation methods.
In addition to obtaining a much higher transconductance gm, since the drain electrode has a stacked structure, it is possible to avoid electric field concentration, and a MOS transistor with excellent hot carrier resistance can be realized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a MOS type semiconductor device that is an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of an embodiment of the method for manufacturing a MOS type semiconductor device of the present invention.

FIG. 3 is a diagram illustrating the configuration of a conventional short channel MOS transistor.

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 N+ type polysilicon layer 5 W or Ti silicide layer 6 Oxide film 7 Gate electrode 8 Protective film 9 Resist pattern 10 n+ type source region 11 n+ type drain region 12 Sidewall 13 Silicide layer 14 Silicide layer

Claims (5)

[Claims] 1. A source region formed by growing a semiconductor substrate of one conductivity type and a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate so as to fill a recess formed by anisotropically etching away the semiconductor substrate; A drain region formed by growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate to a position higher than the channel surface of the semiconductor substrate, and a gate formed between the source region and the drain region with an insulating film interposed therebetween. A MOS type semiconductor device comprising an electrode. 2. A semiconductor layer of a conductivity type opposite to that of the semiconductor substrate grown on a semiconductor substrate of one conductivity type extends continuously on an insulating film existing around a source region or a drain region. 2. The MOS type semiconductor device according to claim 1, wherein the MOS type semiconductor device constitutes a lead wiring of a region or a drain region. 3. A step of anisotropically etching away at least a portion of the semiconductor substrate corresponding to a source region using a gate electrode formed on a semiconductor substrate of one conductivity type as a mask, and a depression removed by the step. At the same time, a step of growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate to a position higher than the channel surface in a portion corresponding to a drain region, and a step of growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate in a portion corresponding to a source region by this step. A method for manufacturing a MOS type semiconductor device, comprising the steps of forming a source electrode and forming a drain electrode on a semiconductor layer grown in a portion corresponding to a drain region. 4. When growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate of one conductivity type, epitaxial growth is performed at a temperature sufficiently low to prevent impurity out-diffusion. A method for manufacturing a MOS type semiconductor device according to claim 3. 5. When growing a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate of one conductivity type, the semiconductor layer is also continuously grown on the insulating film existing around the source region and the drain region. 4. The method of manufacturing a MOS type semiconductor device according to claim 3, wherein a lead wiring for a source region or a drain region is formed by a semiconductor layer grown on the insulating film.