JP2682088B2 - Field effect transistor and method of manufacturing the same - Google Patents
Field effect transistor and method of manufacturing the sameInfo
- Publication number
- JP2682088B2 JP2682088B2 JP31154588A JP31154588A JP2682088B2 JP 2682088 B2 JP2682088 B2 JP 2682088B2 JP 31154588 A JP31154588 A JP 31154588A JP 31154588 A JP31154588 A JP 31154588A JP 2682088 B2 JP2682088 B2 JP 2682088B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- effect transistor
- source layer
- field effect
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 A.産業上の利用分野 本発明は、電界効果トランジスタ及びその製造方法に
関する。The present invention relates to a field effect transistor and a method for manufacturing the same.
B.発明の概要 本発明の電界効果トランジスタは、P-層上部にn+ソー
ス層を設け、このソース層より前記P-層にＶ溝を設け、
このＶ溝面を酸化膜とした電界効果トランジスタにおい
て、前記Ｖ溝を前記ソース層の下面より僅か上に段部が
位置する段付Ｖ溝としてこの段部の下に前記ソース層の
薄い部分を形成すると共に、前記P-層の前記ソース層の
薄い部分より外側部分にP+拡散層を設け、電子電流経路
抵抗を大きくすると共に、ホール電流経路抵抗を小さく
したものである。Field effect transistor of the Summary of the Invention B. invention, P - the n + source layer provided on the layer upper, the P from the source layer - provided a V-groove in the layer,
In the field effect transistor using the V-groove surface as an oxide film, the V-groove is a stepped V-groove having a step slightly above the lower surface of the source layer, and a thin portion of the source layer is formed under the step. Along with the formation, a P + diffusion layer is provided outside the thin portion of the source layer of the P − layer to increase the electron current path resistance and reduce the hole current path resistance.
また、その製造方法は、P-層にP+拡散層を設けた後に
n+ソース層を設け、このソース層に２段に分けてエッチ
ングを行い段付Ｖ溝を設けるようにしたものである。The manufacturing method therefor, P - after providing a P + diffusion layer to the layer
An n + source layer is provided, and the source layer is divided into two stages and etched to form a stepped V groove.
C.従来の技術 従来の竪型MOS電界効果トランジスタ（以下FETとい
う）は、第３図に示すように構成されており、ゲート電
極Ｇに電圧を印加することによって、酸化物SiO2との界
面近傍に薄いＰ層の反転層を形成させ、それにより電子
e-が矢印方向に流れ、ゲート電圧を取り去ると反転層が
蓄積状態となり電子e-は流れなくなる。これにより高速
のスイッチングを行うことができる。MOSFETは竪型にし
たことによりチャネル形成密度が上がり、電流容量が増
す事によって電力用としての用途が開けた。C. Conventional Technology A conventional vertical MOS field effect transistor (hereinafter referred to as FET) is configured as shown in FIG. 3, and by applying a voltage to the gate electrode G, an interface with the oxide SiO 2 is obtained. An inversion layer of a thin P layer is formed near the
e − flows in the direction of the arrow, and when the gate voltage is removed, the inversion layer enters the accumulation state and electrons e − stop flowing. This enables high-speed switching. By making the MOSFET vertical, the channel formation density increased, and the current capacity increased, which opened the application for power.
最近更に消費電力を軽減するために、ON抵抗を下げ、
更に電流容量を上げる試みがなされた。第４図，第５図
にバイポーラ型のMOSFETを示す。これらは電流キャリア
を電子ｅとホールｈにすることによってON抵抗を下げ、
かつ、第５図はゲート位置を低くして電流経路を短縮し
更に抵抗を下げている。Recently, to further reduce power consumption, lower the ON resistance,
Attempts were made to further increase the current capacity. Figures 4 and 5 show bipolar MOSFETs. These reduce the ON resistance by making the current carriers electrons e and holes h,
Moreover, in FIG. 5, the gate position is lowered to shorten the current path and further lower the resistance.
D.発明が解決しようとする課題 ところが、このバイポーラ型の構造では、点線枠ａで
囲まれている部分がサイリスタ構造（寄生サイリスタ）
となり、この寄生サイリスタが、或る印加電圧以上では
ONの状態になるため、ゲート信号によるターン−オフが
できなくなる。この現象はラッチアップと呼ばれる。D. Problem to be Solved by the Invention However, in this bipolar type structure, the portion surrounded by the dotted frame a is a thyristor structure (parasitic thyristor).
Therefore, if this parasitic thyristor exceeds a certain applied voltage,
Since it is turned on, it cannot be turned off by the gate signal. This phenomenon is called latchup.
＜ラッチアップが起こらない条件＞ 寄生サイリスタ部分は、第６図に示すようにnpn接合
とpnp接合の二つのトランジスタを組み合わせた構造と
なっており、各々の電流増幅率が次式（１）を満たす限
りはラッチアップは抑制できる。<Conditions in which latch-up does not occur> The parasitic thyristor part has a structure in which two transistors, an npn junction and a pnp junction, are combined as shown in FIG. Latch-up can be suppressed as long as it is satisfied.
αpnp＋αnpn＜１ …（１） ここで、αnpn＝IC/IE,IE＝IB＋IC これを更に第７図で説明すると、電子e-の経路抵抗RN
とホールh+の経路抵抗RPが並列に存在すると考えられ、
次式（２）を満たす限りラッチアップは起こらない。αpnp + αnpn <1 ... (1 ) where, αnpn = I C / I E , the I E = I B + I C which is further described in FIG. 7, electrons e - of the path resistor R N
And the path resistance R P of the hole h + is considered to exist in parallel,
Latch-up does not occur as long as the following expression (2) is satisfied.
Ih・RP−Ie・RN＜Vb ここで、Ih;ホール電流,Ie;電子電流,Vb;拡散電位差 従って、上記式（１），（２）を満たすためには、 ｉ）Ihを小さくする。 Ih · R P -Ie · R N <Vb where, Ih; hole current, Ie; electron current, Vb; diffusion potential Therefore, the equation (1), in order to satisfy (2), i) the Ih small To do.
ii）RPを小さくする。ii) Reduce R P.
iii）RNを大きくする。iii) Increase R N.
等の工夫が必要である。It is necessary to devise such as.
本発明は、バイポーラ型MOSFETにおいて、ラッチアッ
プが起こらないための条件として前記ii）,iii）項を満
たすことのできる半導体装置及びその製造方法を提供す
るものである。The present invention provides a semiconductor device capable of satisfying the above conditions ii) and iii) as a condition for preventing latch-up in a bipolar MOSFET, and a method for manufacturing the same.
E.課題を解決するための手段 上記目的を達成するために、本発明の電界効果トラン
ジスタは、P-層上部にn+ソース層を設け、このソース層
より前記P-層にＶ溝を設け、このＶ溝面を酸化膜とした
電界効果トランジスタにおいて、前記Ｖ溝を前記ソース
層の下面より僅か上に段部が位置する段付Ｖ溝としてこ
の段部の下に前記ソース層の薄い部分を形成すると共
に、前記P-層の前記ソース層の薄い部分より外側部分に
P+拡散層を設けたものである。In order to achieve the means above object for solving the E. problem, the field effect transistor of the present invention, P - the n + source layer provided on the layer upper, the P from the source layer - provided a V-groove in the layer In the field effect transistor in which the V-groove surface is an oxide film, the V-groove is a stepped V-groove having a step portion slightly above the lower surface of the source layer, and a thin portion of the source layer is under the step portion. To form a P - layer on the outer side of the thin portion of the source layer.
A P + diffusion layer is provided.
そして、前記電界効果トランジスタは、P-層にP+拡散
層を設けた後にn+ソース層を設け、このソース層に２段
に分けてエッチングを行い段付Ｖ溝を設けて製造するの
がよい。The field effect transistor is manufactured by providing a P + diffusion layer on the P − layer, and then providing an n + source layer, and etching the source layer in two steps to provide a stepped V groove. Good.
F.作用 電子電流は、n+ソース層より薄くなったn+ソース層部
分を通ってゲート電極，ゲート酸化膜,P-層により形成
されるｎチャネル層を経てドレイン電極の方に流れる。F. action electron current, the gate electrode through the n + source layer portion becomes thinner than the n + source layer, a gate oxide film, P - flows to the drain electrode through the n-channel layer formed by a layer.
電子電流の流れるn+ソース層とチャネルとの間は薄い
n+拡散層となっているので、ソース層からチャネルに至
る電子電流経路抵抗RNが大きくなる。Thin between n + source layer and channel where electron current flows
Since it is an n + diffusion layer, the electron current path resistance R N from the source layer to the channel becomes large.
ホール電流は、ドレイン電極からシリコン基板,n+エ
ピタキシャル層等を経てP-層からP+層を通ってソース電
極に流れる。このためP-層からソース電極に至るホール
電流経路抵抗RPが小さくなる。The hole current flows from the drain electrode to the source electrode through the silicon substrate, the n + epitaxial layer, and the P − layer to the P + layer. Therefore, the hole current path resistance R P from the P − layer to the source electrode becomes small.
抵抗RNが大きくなり、抵抗RPが小さくなるので、寄生
サイリスタによるラッチアップ現象が起こる電圧が高く
なる。Since the resistance R N becomes large and the resistance R P becomes small, the voltage at which the latch-up phenomenon due to the parasitic thyristor occurs becomes high.
G.実施例 本発明の実施例に係る電界効果トランジスタを製造方
法と共に説明する。G. Example A field effect transistor according to an example of the present invention will be described together with a manufacturing method.
P+シリコン基板１上に、n+エピタキシャル層2,n-エピ
タキシャル層3,P-エピタキシャル層４を順次設ける。P-
層４のゲート構造部分となる部分の外側部分をP+拡散層
５とし、次いでP-層４の上部及びP+拡散層５の上部内側
部分にかけてn+拡散してソース層６を設ける。On the P + silicon substrate 1, the n + epitaxial layer 2, n − epitaxial layer 3 and P − epitaxial layer 4 are sequentially provided. P -
An outer portion of the portion of the layer 4 which becomes the gate structure portion is set as a P + diffusion layer 5, and then a source layer 6 is provided by n + diffusion over the upper portion of the P − layer 4 and the upper inner portion of the P + diffusion layer 5.
次に、ソース層６に２段階に分けてエッチングを行い
P-層４の底部に達する段部７′のある段付Ｖ溝７を設
け、段部７′とP-層４との間に薄いソース層６′部分を
形成する。Next, the source layer 6 is etched in two steps.
A stepped V-groove 7 having a step 7 ′ reaching the bottom of the P − layer 4 is provided, and a thin source layer 6 ′ portion is formed between the step 7 ′ and the P − layer 4.
この段付Ｖ溝７の内面にSiO2ゲート膜８を設け、ゲー
ト酸化膜８にゲート電極９を設ける。そして、ソース層
６とP+拡散層５上にソース電極10を、シリコン基板１の
裏面にドレイン電極11を設けて構成される。A SiO 2 gate film 8 is provided on the inner surface of the stepped V groove 7, and a gate electrode 9 is provided on the gate oxide film 8. Then, the source electrode 10 is provided on the source layer 6 and the P + diffusion layer 5, and the drain electrode 11 is provided on the back surface of the silicon substrate 1.
このように構成された電界効果トランジスタは、ソー
ス層６の下部が薄く構成されているので、ソース電極と
ｎチャネル層４′間の電子電流経路抵抗RNが大きくな
り、又ホール電流はP-層４からP+拡散層５を通ってソー
ス電極10に流れるので、ホール電流経路抵抗RPが小さく
なる。In the field effect transistor having such a structure, since the lower portion of the source layer 6 is made thin, the electron current path resistance R N between the source electrode and the n-channel layer 4 ′ becomes large, and the hole current becomes P −. Since the current flows from the layer 4 through the P + diffusion layer 5 to the source electrode 10, the hole current path resistance R P becomes small.
従って、前記ii）及びiii）項の条件を満たすことが
でき、第２図のように、本発明の電界トランジスタａ
は、ラッチアップ現象の起こる電圧VFを従来同タイプの
電界効果トランジスタｂに比し大幅にアップさせること
ができた。Therefore, the conditions of the above items ii) and iii) can be satisfied, and as shown in FIG.
Can significantly increase the voltage VF at which the latch-up phenomenon occurs as compared with the field-effect transistor b of the same type in the related art.
なお、上記実施例ではP-層をエピタキシャル層とし、
ソース層を拡散層としているが、P-層を拡散層とし、ソ
ース層をイオン注入によるものにするなど、適宜変更し
うることはいうまでもない。In the above embodiment, the P − layer is an epitaxial layer,
Although the source layer is the diffusion layer, it goes without saying that the P − layer may be the diffusion layer and the source layer may be formed by ion implantation.
H.発明の効果 本発明は、上述のとおり構成されているので、電子電
流経路抵抗が大きくなり、又ホール電流経路抵抗が小さ
くなるので、寄生サイリスタによるラッチアップ現象の
起きる電圧を大幅に高くすることができる。H. Effect of the Invention Since the present invention is configured as described above, the electron current path resistance increases and the hall current path resistance decreases, so that the voltage at which the latch-up phenomenon due to the parasitic thyristor occurs is significantly increased. be able to.
第１図は本発明の実施例を示す正断面図、第２図はラッ
チアップ現象の起こる電圧曲線図、第３図乃至第５図は
夫々異なる従来電界効果トランジスタを示す正断面図、
第６図は寄生サイリスタの構成図、第７図（ａ）は電子
電流及びホール電流経路説明図、第７図（ｂ）は経路抵
抗説明図である。 １……P+シリコン基板、４……P-エピタキシャル層、５
……P+拡散層、６……n+ソース層、７……段付Ｖ溝、８
……ゲート酸化膜。1 is a front sectional view showing an embodiment of the present invention, FIG. 2 is a voltage curve diagram in which a latch-up phenomenon occurs, and FIGS. 3 to 5 are front sectional views showing different conventional field effect transistors,
FIG. 6 is a configuration diagram of a parasitic thyristor, FIG. 7 (a) is an electron current and Hall current route explanatory diagram, and FIG. 7 (b) is a route resistance explanatory diagram. 1 …… P + silicon substrate, 4 …… P - epitaxial layer, 5
...... P + diffusion layer, 6 …… n + source layer, 7 …… stepped V groove, 8
...... Gate oxide film.
Claims (2)
層より前記P-層にＶ溝を設け、このＶ溝面を酸化膜とし
た電界効果トランジスタにおいて、 前記Ｖ溝を前記ソース層の下面より僅か上に段部が位置
する段付Ｖ溝としてこの段部の下に前記ソース層の薄い
部分を形成すると共に、前記P-層の前記ソース層の薄い
部分より外側部分にP+拡散層を設けたことを特徴とする
電界効果トランジスタ。1. A P - the n + source layer provided on the layer upper, the P from the source layer - the V-groove layer is provided, in the V-groove surface field effect transistor having an oxide film, the said V-groove A thin portion of the source layer is formed below the step portion as a stepped V-groove having a step portion slightly above the lower surface of the source layer, and the P − layer is provided outside the thin portion of the source layer. A field-effect transistor having a P + diffusion layer.
設け、このソース層に２段に分けてエッチングを行い段
付Ｖ溝を設けることを特徴とした請求項（１）記載の電
界効果トランジスタの製造方法。Wherein P - layers in the n + source layer provided after providing a P + diffusion layer, claim that is characterized by providing a stepped V-grooves etched in two stages in the source layer ( 1) A method for manufacturing a field effect transistor as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31154588A JP2682088B2 (en) | 1988-12-09 | 1988-12-09 | Field effect transistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31154588A JP2682088B2 (en) | 1988-12-09 | 1988-12-09 | Field effect transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02156677A JPH02156677A (en) | 1990-06-15 |
| JP2682088B2 true JP2682088B2 (en) | 1997-11-26 |
Family
ID=18018525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31154588A Expired - Lifetime JP2682088B2 (en) | 1988-12-09 | 1988-12-09 | Field effect transistor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2682088B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4680495B2 (en) * | 2003-12-09 | 2011-05-11 | 株式会社豊田中央研究所 | Semiconductor device |
-
1988
- 1988-12-09 JP JP31154588A patent/JP2682088B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02156677A (en) | 1990-06-15 |
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