JP3142009B2 - Manufacturing method of electrostatic induction type gate structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION Surface gates for high-speed, high-efficiency switching semiconductor devices, especially for static induction thyristors and static induction transistors, realizing high-speed switching performance and high gate breakdown voltage without impairing manufacturing stability. The present invention relates to a method for manufacturing an electrostatic induction type gate structure having a structure.

[0002]

2. Description of the Related Art A conventional electrostatic induction thyristor (hereinafter SI)
Thyristor), static induction type transistor (hereinafter S
FIGS. 13 to 15 show schematic sectional structural views of the same (referred to as IT). 13 shows an example of a buried gate type structure, FIG. 14 shows an example of a notched gate type structure, and FIG. 15 shows an example of a surface gate type structure. 13 to 15, 1 is a cathode electrode (source electrode), 2 is a gate electrode, 3 is an anode electrode (drain electrode), 4 is an n emitter (n _E ) (source) diffusion layer, and 5 is n in an epitaxial growth layer. ^- layer, p gate diffusion layer 6 (p _B), 7 the n ^- or i (intrinsic) substrate, 8 p
Emitter diffusion layer, 9 is a SiO ₂ insulating film, 10 is an n-channel, 11 is a region removed by etching, 12 is an epitaxial growth layer, 13 is a capacitance near a gate, and 14 is p _B
Indicates the resistance r _s between −n _E.

[0003] () corresponds to the case of SIT.
Hereinafter, the case of the SI thyristor will be described for the sake of simplicity.

FIG. 13 shows a paper by Muraoka et al.
"Characteristics of 1600V, 300A SI thyristor" IEEJ document EDD-88-56, SPC-88-54, 67 (1988) or Tatsuta et al., "Characteristics of high frequency power SIT" IEEJ document EDD-87-68 , SPC-87-52, 61 (1987). FIG. 14 shows, for example, H. Gru
Ening et al., “Field Controlled Thyristors
a New-Family of PowerSemiconductors with Advanced
Circuitry "Conf. Rec., PESC '88, 1311 (1988). Alternatively, FIG.
See, for example, a paper by Tadano et al., “Switching Characteristics of Short-Circuited SI Thyristors,” IEEJ EDD-90-59, SPC
-90-58 (1990).

Focusing on the cathode electrode side structure, the advantages and disadvantages of the conventional device are as follows. The buried gate type structure of FIG. 13 includes a step of growing an n ⁻ epitaxial layer 12 on the cathode side and removing the deleted region 11 by etching. As an advantage, the thickness of the epitaxial layer between the cathode and the gate can be increased, so that the gate-cathode breakdown voltage can be increased. For example, about 70 to 200 V can be easily obtained. Accordingly, the production yield is high, and the cathode can be pressed and sealed and assembled in a pressure-bonding type package, and its main use is to use it as a high-power switching element. However, as a disadvantage, in this type, the thickness of the epitaxial layer 12 is increased for power, but the gate diffusion layer (p _B
It is difficult to form a stable high resistance n ⁻ layer 5 by out diffusion from the layer 6 or the substrate, and usually N _B = 1
It is formed at about 4 × 10 ¹⁵ cm ⁻³ .

[0006] The capacitance formed between the gate and the cathode is the

[0007]

[Number 1] _{C g = {(qε 0 ε} s N B) / (2 (V bi -V)} 1/2 ··· (1)

## EQU1 ## Here epsilon ₀ is the vacuum dielectric constant, epsilon _s is the dielectric constant of Si, N _B epitaxial layer n-type impurity concentration, the V _bi built-in potential, V is a reverse bias (minus) voltage.

[0009] The value of the capacitance C _g represented by the equation (1), ideally n ^- than the layer high resistance, i.e., when i stratification (e.g. ^{_{N B <1 × 10 13 cm}} -3) growing. That when the SI thyristor in the ON state, the charging time giving the limit of static induction effect (time constant) τ = C _g × r _s increases. Here, the current flowing in the RC circuit system is

[0010]

(Equation 2)

Then, V ₀ is a charging voltage, r _s is a resistance,
t is time, r _s is Energized resistance between n emitter diffusion layer (n _E) 4 and a p gate diffusion layer (p _B) 6. Therefore, a device of this type has a significantly increased turn-on time as the thickness of the epitaxial layer 12 increases,
Speeding up is limited due to device performance.

In addition, when the epitaxial layer is made thick, it is difficult to miniaturize the cathode, and a large number of channels 10 are arranged as a current conduction region, so that a delay occurs when current is drawn from the gate electrode 2. That is, a region having poor controllability by the gate voltage is formed in the central region of the unit segment. Therefore, since the turn-off performance is also limited, the epitaxial layer 12 is intended for power devices, but the high-speed performance is inferior and high-speed cannot be expected.

The notched gate type structure shown in FIG. 14 includes a step of cutting the n ^- substrate 7 by dry etching to form a vertically long channel 10. This length reaches, for example, about 25 μm.

This type can be operated at high speed by performing fine processing, but is disadvantageous to the ON performance only because the channel is long in the vertical direction, and at the same time, is coplanar with the plane of the n emitter diffusion layer (n _E ) 4. A junction with the p-gate diffusion layer (p _B ) has been made, and a junction with a high concentration is formed. Therefore, a high electric field is applied to the junction, and the breakdown voltage is only about 7 to 25 V. This is peculiar to the planar type and is a common problem with FIG. 15. It is difficult to obtain a uniform and stable gate-cathode breakdown voltage in manufacturing. It is a major drawback that it is easily broken by spike voltage or the like.

The planar structure shown in FIG. 15 includes a step of providing a cathode electrode 1 and a gate electrode 2 on substantially the same surface. Advantageously, the electrostatic capacitance C _g is formed between the gate and the cathode is small, ON performance is most superior. In general, to improve the OFF performance of a thyristor, the anode short-circuit rate is increased or a lifetime control is used. However, even if the OFF performance of a device having excellent ON performance is improved, the change in ON performance is small or negligible. In the planar gate structure, the cathode side can be miniaturized most, a large current carrying area can be obtained, and the area utilization rate is high.
Also, a gate electrode can be placed right next to the channel,
The resistance of the current to the gate electrode is low, and the turn-off OFF performance is excellent.

[0016] However, as disadvantage, since the n _E layer 4 and the p _B layer 6 like the cut-gate structure shown in FIG. 14 is a planar connection having bonding high density between the cathode electrode 1, the gate The withstand voltage between the electrodes 2 can be at most about 25V.

Furthermore, the channel width cannot be made wide (a few μm).
m) and the like, and it is necessary to accurately arrange the p _B layer 6 and the n _E layer 4. When both layers deviate from the predetermined position, p
Disadvantages such as the concentration gradient of the junction is particularly steep occurs between _B -n _E, the breakdown voltage is further reduced. Generally, the alignment accuracy of the conventional planar type is 0. Several μm is required, and it is very difficult to stabilize production. Therefore, similarly to the structure shown in FIG. 14, there is a problem in terms of yield and in that it is easily broken during use.

In the conventional planar gate structure, alignment accuracy and finished dimensional accuracy on the gate side are strictly required for the following reasons. First, electrostatic induction type element the specified voltage applied between the anode and the cathode in the forward direction, the gate potential of the gate near i.e., for example, p _B -n _E a reverse bias is applied between the built-in potential or the gate and cathode occurs between Block (block) with voltage. Here, the voltage amplification factor μ is defined as the gate voltage with respect to the anode voltage to be controlled. Therefore, the finished size near the gate is 0.1 mm. Several micrometers are required. Moreover, the constraints on the dimensions, will close forming a p _B diffusion layer 6 and the n _E diffusion layer 4. As a result, a "p ⁺ -n ⁺ junction" between the high concentration diffusion layers is formed near the surface of the gate diffusion layer. When a reverse bias voltage is applied to this junction, a so-called reverse breakdown voltage between the gate and the cathode is such that a strong electric field is concentrated at a junction having a sharp concentration difference, and thus a break-over occurs at a low bias voltage (for example, about 25 V). Would. Also in this case, the steep concentration gradient of the “p ⁺ −n ⁺ junction” changes due to the difference in finished dimensional accuracy, and the reverse breakdown voltage between the gate and the cathode changes, resulting in a finished product.

For this reason, the planar gate structure requires extremely strict processing accuracy and is manufactured by making full use of techniques such as a stepper exposure method and a self-alignment technique. However, the yield does not increase moderately. It is a fact. Further, in a dimensional design that is practical, the reverse breakdown voltage between the gate and the cathode is at most about 25 V. When applied to a device, local destruction is likely to occur due to spike voltage during actual operation. Therefore, the conventional planar gate structure is disadvantageous, especially in the direction of power devices.

[0020]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a new method of manufacturing a planar electrostatic induction gate structure.

It is a further object of the present invention to provide a manufacturing method capable of realizing a high gate breakdown voltage and a high manufacturing yield in a planar electrostatic induction type gate structure.

[0022]

SUMMARY OF THE INVENTION The present invention is directed to improving the reverse breakdown voltage between the gate and the cathode, and providing a margin in the finished dimension between the gate and the cathode to facilitate manufacture. and forming a thin epitaxial layer as compared to the p _B diffusion depth. This p-type impurity from the p _B diffusion layer during the high temperature epitaxial growth out Day fusion, and the channel compensation by n-type impurities so as not to fully closed, p from the interface the start of the epitaxial growth, toward the cathode side surface of the epitaxial growth ends _A step of finishing the _B diffusion layer 6 in a manner similar to the gate shape of the buried gate type, that is, a so-called impurity concentration gradient until it contacts the n _E diffusion layer 4 to be formed later and the concentration are lower and lower than those of the conventional planar type. It is characterized by forming.

The constitution of the present invention is as shown below. That is, the present invention is a method of manufacturing a planar electrostatic induction type gate structure in which a gate diffusion layer and an emitter diffusion layer facing the gate diffusion layer are formed on the same plane. Forming an epitaxial growth layer so as to form a shaped gate structure, and performing auto-doping of gate diffusion impurities during the formation of the epitaxial growth layer, and compensating for auto-doping to form an emitter diffusion layer and a gate diffusion layer formed on the surface of the epitaxial growth layer. Forming a pin junction sandwiching a high-resistance layer in which p-type and n-type impurities are compensated for by substantially equal amounts between the layers and a gate diffusion layer buried after the formation of the epitaxial growth layer A step of additionally diffusing an impurity for forming a semiconductor of the same conductivity type as the gate impurity on the top, and forming a gate electrode on the epitaxial surface Characterized in that comprising the that step,
It has a configuration as a method of manufacturing an electrostatic induction type gate structure.

[0024]

The structure according to the present invention to which epitaxial growth is applied is changed to a planar epitaxial gate (Planar Epitaxi).
al Gate, PEG).

FIGS. 7 to 9 show a typical structure of p _B -n _E.
The profile of the p-type and n-type impurities and the profile of the resistance value (R _s ) by the spreading resistance method in the depth direction at the junction, where the reverse breakdown voltage ( _VRGM ) is determined, are shown.

The section AA 'in FIG. 7 shows a profile in which V _RGM = 60 to 200 V is obtained in the case of the buried gate type structure shown in FIG. In this case, since there is a thick epitaxial layer between p _B -n _E, high breakdown voltage can be obtained optionally. However, in application to an actual device, the necessary and sufficient V _RGM is at most about 60 V, and this structure is likely to cause a variation in gate resistance due to a gate digging step, and is likely to cause a reduction in element performance. Also directly, as planar structures, it is difficult to metal wiring p _B layer throughout a special structure is required. The difficulty in lowering the gate resistance from manufacturing variations limits the performance of SI thyristors and SITs, which should have low gate resistance.

The cross section BB 'in FIG. 8 shows a profile in which V _RGM = 25 V is obtained in the case of the planar structure shown in FIG. This is an example in the case of a normally-off type, and there is not much difference in breakdown voltage from a GTO thyristor. this is,
In order p _B layer and the n _E layer is in contact with a high concentration together, because a high electric field and short joint is concentrated. Also 0. Several μ
Due to the variation in the alignment accuracy of m, a junction is formed in which it is more difficult to obtain a withstand voltage. In addition, various types of joining can be easily performed depending on locations. In other words, when applied to an apparatus, there is a great feature that local destruction is easily caused and the production yield is low.

The cross section CC 'in FIG. 9 in the case of the PEG of the invention, for providing the gate electrode 2 in the epitaxial growth layer, and a p _E layer 6 and the n _E layer 4 is low density - in contact at a low concentration gradient Therefore, a high-resistance i-layer is formed in a thickness of about 1.5 μm to form a pin structure. For this reason, the electric field has a cross section BB '.
V _RGM = 6
There is a feature that the breakdown voltage is improved to 0V. Also with respect to the pattern shift, since between p _B -n _E meet at low concentrations among the performance of the pin structure is not almost the same. In other words, there is a great feature that stabilization can be achieved even with process variations, and a required and sufficient breakdown voltage comparable to that of the embedded gate type can be secured. Although using epitaxial growth,
P _B layer 6 directly metal electrode gate digging etch is not required
, The gate resistance is reduced ideally as in the planar type. That is, the speed is increased and the breakdown strength is high.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a process flow for realizing the present invention will be described with reference to a planar gate structure of an SI thyristor shown in FIGS. 1 to FIG.
Reference numeral 4 designates the same area as the conventional example with the same number. That is,
1 is a cathode electrode, 2 is a gate electrode, and 3 is an anode electrode. 4 is an n emitter (n _E ) diffusion layer, 5 is an n ⁻ layer in the epitaxial growth layer, 6 is a p gate diffusion layer (p _B ),
7 ⁿ - (i) a substrate, 8 is p emitter diffusion layer, 9 Si
An O ₂ insulating film, 10 is an n-channel, 11 is a region removed by etching, 12 is an epitaxial growth layer, 13 is a capacitance near a gate, and 14 is a resistance r _s between p _{B and} n _E.
Further, 9 'denotes an SiO ₂ film, 15 denotes SiNx, and a polyimide insulating film.

Referring to FIGS. 1 to 6, the following (i) to (v)
In i), the manufacturing method will be sequentially described.

[0031] In (i) Figure 1, n ^- in the substrate 7, a photolithography process, to form in selective boron diffusion of p _B diffusion layer 6. The diffusion depth is 5 μm.

[0032] In (ii) 2, whereas n ^- conducting the epitaxial growth form (= 4Ω-cm). In the epitaxial growth, following the HCl gas etching for surface cleaning, the epitaxial growth was performed at a growth temperature of 1180 ° C. at a growth rate of 0.18 μm / min using SiCl ₄ gas, PH ₃ as a compensation gas, and H ₂ as a carrier gas. Perform 5 μm. Since the n-channel 10 not closed by the p _B layer, during the epitaxial growth, the boron atoms out Day fusion than p _B layer 6 (B), to compensate for the substantially equal amount of phosphorus atoms (P), the channel 10 near the In particular, it has an i-layer. Also with the progress of the epitaxial growth, the area of the p _B layer 6 so out Day fusion also reduces the boron atoms (B) decreases as it approaches the cathode surface. Concentration gradient and the concentration of p _B layer 6 surface and the depth direction is thinner at the junction near the surface, and loose.

[0033] In (iii) 3, possible to improve the ohmic contact between the p _B layer 6 and the gate electrode 2, and by lowering the gate lead resistors, to operating speed. Therefore, after epitaxial growth, oxidation is performed, a selective window is opened in the center of the _pB layer 6, and boron or a p-type impurity is additionally diffused to form a p-gate ohmic diffusion layer 6 '. In addition, SiH ₄ and SiH ₂ Cl are used as epitaxial growth gases.
₂ , the same structure can be formed by using SiHCl ₃ .

(Iv) In FIG. 4, next, n
Re-oxidize to provide the _E diffusion layer area,
A selective window is opened in the oxide film on the substrate 0 to diffuse phosphorus or n-type impurities. The depth is about 1 μm.

(V) In FIG. 5, a selective window is opened in the SiO ₂ film on the p _B layer to provide the gate electrode 2.
Al deposition is performed on the entire surface to be selectively left at the gate portion, and the portion is selectively insulated by SiN by CVD and an insulating resin film such as polyimide.

(Vi) In FIG. 6, after that, Al deposition is performed as a cathode electrode on the entire surface to form a cathode electrode.

The description of the anode-side processing is made in accordance with the structures of the target transistor and thyristor, respectively, but the description is omitted here.

As described above, in this structure, as compared with the conventional planar type, a distance between the n _E layer and the p _B layer can be provided by the use of the epitaxial layer, and the impurity concentration at the junction can be increased. The gradient is reduced, during which an i-layer with higher resistance closer to the intrinsic is reliably formed. When the concentration gradient is large between the high concentrations at the junction, the i-layer is hardly formed because the high doping deteriorates the crystallinity.

An example in which the embodiment according to the present invention is specifically applied will be described below.

FIG. 10 shows that PE according to the present invention is provided on the cathode side.
FIG. 2 shows a schematic cross-sectional structure diagram of an SI thyristor provided with a G structure and using an SI anode short structure on the anode side.

FIG. 11 is a schematic sectional view of a SIT having the present PEG structure on the source side.

FIG. 12 shows a double gate SI thyristor in which the first gate electrode on the cathode side is made of ap ⁺ diffusion layer and the second gate electrode on the anode side is provided with an n ⁺ diffusion layer. The second gate side has a junction opposite to that described above (gate: n ⁺ , anode: p ⁺ ) but PEG
The mold structure applies exactly the same. Particularly in a double gate SI thyristor, strict processing accuracy is required for both the front and back sides of the wafer substrate, so that the PEG structure according to the present invention is advantageous. Although the arrangement pitch is 15 μm, the device area can be effectively used without changing to the conventional planar shape. In each figure, 16 is the second gate electrode, 17 is the anode n ⁺ short layer, and 18 is the drain n
⁺ Diffusion layer, 19 is the second gate n ⁺ diffusion layer, 19 ′ is the second gate
Gate n ⁺⁺ additional diffusion layer, 20 is a source electrode, 21 is a drain electrode. Note that, for 1 to 15, the same numbers are given to the same parts as those in the conventional example and the embodiment shown in FIGS.

[0043]

According to the present invention, a high production yield and a higher gate breakdown voltage can be obtained without using advanced production equipment such as a stepper by increasing the switching speed of the planar type and the tolerance of the processing accuracy. The present invention relates to a method for manufacturing an electrostatic induction type gate structure. In that regard, 1200V / 30A
Class single gate SI thyristor, conventional type and PEG
Table 1 shows the comparison with the shape.

[0044]

[Table 1]

As described above, an excellent static induction type gate structure having a high gate breakdown voltage, a high yield, and the same switching speed as that of the conventional planar type can be realized.

[Brief description of the drawings]

FIG. 1 is a process chart for forming a p-gate diffusion layer on an n ⁻ (i) substrate.

FIG. 2 is an epitaxial process drawing with phosphorus compensation.

FIG. 3 is a process chart of ohmic diffusion for a gate.

FIG. 4 is a process chart of forming a cathode diffusion layer (n _E ).

FIG. 5 is a process chart of forming a gate electrode.

FIG. 6 is a process chart of forming a cathode electrode.

FIG. 7 shows the sheet resistance R _s and the impurity density distribution in the AA ′ direction of FIG. 13 (conventional example).

8 shows the sheet resistance R _s and the impurity density distribution in the direction BB ′ of FIG. 15 (conventional example).

FIG. 9 shows the sheet resistance R _s and the impurity density distribution in the CC ′ direction of FIG. 6 (the present invention).

FIG. 10 shows an application example of the present invention to an SI thyristor having a planar gate type and an SI anode short structure.

FIG. 11 shows an application example of the present invention to a planar gate type SIT.

FIG. 12 shows an application example of the present invention to a double-gate SI thyristor.

FIG. 13 shows a schematic cross-sectional structure diagram of a conventional embedded gate type SI thyristor.

FIG. 14 is a schematic sectional structural view of a conventional notched-gate SI thyristor.

FIG. 15 is a schematic cross-sectional view of a conventional surface-gate SI thyristor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 cathode (source) electrode 2 gate electrode 3 anode (drain) electrode 4 n emitter (source) (n _E ) diffusion layer 5 n ⁻ layer in epitaxial growth layer 6 p gate diffusion layer (p _B ) 6 ′ p gate ohmic diffusion layer 7 n ^- (i) a substrate 8 p-emitter (anode, drain) diffusion layers 9, 9 'SiO ₂ film 10 n-channel 11 removed by the etching region 12 epitaxially grown layer 13 near the gate capacitance 14 p _B -n _E between resistor r _s 15 SiNx and polyimide insulating film 16 second gate electrode 17 anode n ⁺ short layer 18 drain n ⁺ diffusion layer 19 second gate diffusion layer 19 ′ second gate n ⁺⁺ additional diffusion layer 20 source electrode 21 drain electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/74 H01L 29/80

Claims (1)

(57) [Claims] 1. A method for manufacturing a planar electrostatic induction type gate structure, wherein a gate diffusion layer and an emitter diffusion layer facing the gate diffusion layer are formed on the same plane. Forming an epitaxial growth layer so as to form a gate structure; and, during formation of the epitaxial growth layer, performing auto-doping of gate diffusion impurities and compensating for auto-doping, and forming an emitter diffusion layer and a gate diffusion layer formed on the surface of the epitaxial growth layer. Forming a pin junction sandwiching a high-resistance layer in which p-type and n-type impurities are compensated by substantially equal amounts, and after the formation of the epitaxial growth layer, Additionally diffusing an impurity for forming a semiconductor of the same conductivity type as the gate impurity into the surface of the epitaxial growth layer; Method of manufacturing a static induction type gate structure, characterized in that comprising the step of forming a.