JPH02184078A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPH02184078A JPH02184078A JP408589A JP408589A JPH02184078A JP H02184078 A JPH02184078 A JP H02184078A JP 408589 A JP408589 A JP 408589A JP 408589 A JP408589 A JP 408589A JP H02184078 A JPH02184078 A JP H02184078A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- source
- electrode
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000282806 Rhinoceros Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 Ａ、産業上の利用分野 本発明は、電界効果トランジスタに関する。[Detailed description of the invention] A. Industrial application field The present invention relates to field effect transistors.
８９発明の概要
本発明の電界効果トランジスタは、堅型バイポーラＭＯ
９ＦＥＴ又は堅型バイポーラＶＭＯＳＦＥ’ｒにおいて
、ｎ゛ソース層ｎ −ＧａＡｓエピタキシャル層とし
、これが設けられるＰエピタキシャル層との間にＰ−ｎ
へテロ接合を作り、ホールに対する障壁を高くすると共
に、Ｐエピタキシャル層にＰ゛拡散層を設け、これにソ
ース電極を接合して、ホールがこのＰ０拡散層を通って
ソース電極に良く流れるようにしたものである。89 Summary of the Invention The field effect transistor of the present invention is a hard bipolar MO
In a 9FET or rigid bipolar VMOSFE'r, an n source layer is an n-GaAs epitaxial layer, and a P-n layer is formed between this and a P epitaxial layer.
In addition to creating a heterojunction and increasing the barrier to holes, a P diffusion layer is provided in the P epitaxial layer and a source electrode is bonded to this so that holes can flow well through this P diffusion layer to the source electrode. This is what I did.
Ｃ１従来の技術
従来の堅型ＭＯＳ電界効果トランジスタ（ＦＥＴ）は、
第４図に示すように構成されており、ゲ−ト電極Ｇに電
圧を印加することによって、酸化物Ｓ Ｉ Ｏｔとの界
面近傍に薄いＰ層の反転層を形成させ、それにより電子
Ｃ−が矢印方向に流れ、ゲート電圧を取り去ると反転層
が蓄積状態となり電子ｅ−は流れなくなる。これにより
高速のスイッチングを行うことができる。０Ｍ５ＦＥＴ
は竪形にしたことによりチャネル形成密度が上がり、電
流容量が増す事によって電力用としての用途が開けた。C1 Conventional technology The conventional rigid MOS field effect transistor (FET) is
It is constructed as shown in FIG. 4, and by applying a voltage to the gate electrode G, an inversion layer of a thin P layer is formed near the interface with the oxide S I Ot, thereby inverting the electron C- flows in the direction of the arrow, and when the gate voltage is removed, the inversion layer becomes in an accumulation state and electrons e- no longer flow. This allows high-speed switching to be performed. 0M5FET
By making it vertical, the density of channel formation increased, and the current capacity increased, opening up applications for electric power.
最近更に消費電力を軽紘するために、ＯＮ抵抗を下げ、
更に電流容量を上げる試みがなされた。Recently, in order to further reduce power consumption, the ON resistance has been lowered,
Attempts were made to further increase the current capacity.
第５図及び第６図に堅型バイポーラＭＯ８ＦＥＴ及び堅
型バイポーラＶＭＯ８ＦＥＴを示す。これらは電流キャ
リアを電子ｅとホールｈにすることによってＯＮ抵抗を
下げ、かつ第６図はＶ溝を設はゲート位置を低くして電
流経路を短縮し更に抵抗を下げている。5 and 6 show a rigid bipolar MO8FET and a rigid bipolar VMO8FET. These reduce the ON resistance by using electrons e and holes h as current carriers, and in FIG. 6, a V groove is provided and the gate position is lowered to shorten the current path and further reduce the resistance.
Ｄ０発明が解決しようとする課題
ところが、この堅型バイポーラの構造では、点線枠ａで
囲まれている部分がサイリスク構造（寄生サイリスク）
となり、この寄生サイリスタが、成る印加電圧量］−，
ではＯＮの状態になるため、ゲート信号によるターンオ
フができなくなる。この現象はラッチアップと呼ばれる
。Problem to be solved by the D0 invention However, in this rigid bipolar structure, the part surrounded by the dotted line frame a has a cyrisk structure (parasitic cyrisk).
Then, this parasitic thyristor has the applied voltage ]−,
Since it is in the ON state, it cannot be turned off by the gate signal. This phenomenon is called latch-up.
〈ラッチアップが起こらない条件〉
寄生サイリスク部分は、第７図に示すようにｎｐｎ接合
とｐｎｐ接合の２つのトランジスタを組み合わせた構造
となっており、各々の電流増幅率が次式（１）を満たす
限りはラッチアップは抑制できる。<Conditions under which latch-up does not occur> As shown in Figure 7, the parasitic silicon risk part has a structure that combines two transistors, an npn junction and a pnp junction, and the current amplification factor of each satisfies the following equation (1). As long as the requirements are met, latch-up can be suppressed.
αｐｎｐ＋αｎｐｎ＜ｌ ・・ψ（１）ここで、ａｎ
ｐｎ＝Ｉｃ／Ｅｇ、Ｉｇ＝Ｉａ＋Ｉｃこれを更に第８図
で説明すると、電子ｅ−の経路抵抗ＲＮとホール、ｈｏ
の経路抵抗Ｒｐが並列に存在すると考えられ、次式（２
）を満たず限りラッチアップは起ごらない。αpnp+αnpn<l ・・ψ(1) Here, an
pn=Ic/Eg, Ig=Ia+Ic To further explain this with FIG. 8, the path resistance RN of electron e- and hole, ho
It is considered that the path resistance Rp exists in parallel, and the following equation (2
), latch-up will not occur.
！１・ＲＰ−！、・Ｒ，４くｖｌ、 ・ ・ ・ （２
）ここで、！７；ホール電極、！、；電子電流。! 1・RP-! ,・R,4kuvl, ・ ・ ・ (2
)here,! 7; Hall electrode! , ;electronic current.
ｖ２；ビルトイン電位差
従って、上記式（１）、（２）を満たず工夫が必要であ
る。v2: Built-in potential difference Therefore, the above formulas (1) and (2) are not satisfied, and some measures are required.
本発明は、堅型バイポーラＭ ＯＳ Ｆ Ｅ ’ｒ又は
堅型バイポーラＶＭＯＳＦＥＴにおいて、寄生サイリス
タ構造のラッチアップ電圧を高くする目的で、上記式（
２）の■。を大きくした電界効果トランジスタを提供す
ることにある。The present invention uses the above formula (
2) ■. It is an object of the present invention to provide a field effect transistor with a large size.
■シ０課題を解決するための手段
上記［１的を達成するために、本発明の電界効果トラン
ジスタは、Ｐ層上部にｎ゛ソース層設け、このｎ°ソー
ス層から前記Ｐ層にかけてソース電極を接合してなる堅
型バイポーラＭＯ８ＦＥＴ又は堅型バイポーラＶＭＯ８
ＰＥＴにおいて、面記ｎ゛ソース層を、ｎ −ＧａＳ
ｉエピタキシャル層とすると共に、前記Ｐ層の反転層よ
り離れた位置の上部にＰ゛拡散層を設け、前記ソース電
極を前記ｎ −ＧａＡｓエピタキシャル層及びＰ″″
拡散上に接合してなるものである。■Means for Solving Problem 0 In order to achieve object 1 above, the field effect transistor of the present invention has an n source layer provided above the P layer, and a source electrode extending from the n source layer to the P layer. Rigid bipolar MO8FET or rigid bipolar VMO8 made by joining
In PET, the planar n source layer is made of n-GaS
In addition to forming an i epitaxial layer, a P diffusion layer is provided above the P layer at a position away from the inversion layer, and the source electrode is connected to the n-GaAs epitaxial layer and the P''''.
It is formed by bonding on diffusion.
Ｆ９作用
電子はｎ −ＧａＡｓエピタキシャル層からｎチャネ
ルに注入されドレイン側に流れる。F9 working electrons are injected into the n channel from the n -GaAs epitaxial layer and flow toward the drain side.
ｎ −ＧａＡｓエピタキシャル層とＰ層間のホールに
対する障壁は、従来ｎ −３ｉ層とのＰ層間の障壁よ
り０．３ｅＶ程高くなっているので、ホールの流れのブ
ロック効果が大きくなる。Since the barrier to holes between the n-GaAs epitaxial layer and the P layer is about 0.3 eV higher than the conventional barrier between the n-3i layer and the P layer, the effect of blocking the flow of holes is increased.
Ｐ層とソース電極間にはＰ°拡散層があるので、ホール
はＰ“拡散層を通ってソース電極へ流れる。Since there is a P° diffusion layer between the P layer and the source electrode, holes flow to the source electrode through the P'' diffusion layer.
Ｇ、実施例
本発明の実施例にかかる電界効果トランジスタをその製
造方法と共に説明する。G. Example A field effect transistor according to an example of the present invention will be described together with a method for manufacturing the same.
第１図において、Ｐ゛シリコン基板ｌ上に、ｎエピタキ
シャルｆｉ２’、ｎ−エピタキシャル層３゜Ｐエピタキ
シャル層４を順次設ける。この２層４の北部に所定間隔
でＰ°拡散層５．５を設け、このＰ′″層５，５に跨が
るように２層４の上面にｎ−ＧａＡｓのエピタキシャル
層６を形成し、Ｐ−ｎヘテロ接合を作る。In FIG. 1, an n epitaxial layer fi2', an n-epitaxial layer 3, and a P epitaxial layer 4 are sequentially provided on a P silicon substrate l. P° diffusion layers 5.5 are provided at predetermined intervals in the northern part of the two layers 4, and an n-GaAs epitaxial layer 6 is formed on the upper surface of the two layers 4 so as to straddle the P'' layers 5,5. , creating a P-n heterojunction.
このｎ７ＧａＡｓ層６の中央部に■溝７を設け、このＶ
１Ｉ１４７からｎ −ＧａＡｓ層の内端−上面にか
けてＳ ｉ Ｏ！ゲート酸化膜８を施す。そして、ゲー
ト酸化膜８のＶ溝部分にゲート電極９を設けると共に、
ｎ −ＧａＡｓ層６からＰ°層５及び２層４にかけて
ソース（エミッタ）電極１０を設け、Ｐ″基板Ｉの裏側
にドレイン電極１１を設けて構成されている。A groove 7 is provided in the center of this n7GaAs layer 6, and this V
S i O! from 1I147 to the inner end-top surface of the n-GaAs layer. A gate oxide film 8 is applied. Then, a gate electrode 9 is provided in the V-groove portion of the gate oxide film 8, and
A source (emitter) electrode 10 is provided from the n-GaAs layer 6 to the P° layer 5 and the second layer 4, and a drain electrode 11 is provided on the back side of the P'' substrate I.
このように、本発明の電界効果トランジスタは構成され
ているので、電子電流１．は、ｎ−ＧａＡｓ層６からゲ
ート電極９．ゲート酸化膜８，２層４により形成される
ｎチャンネル４′に注入され、ｎ”層３．ｎ°層２．Ｐ
０基板１．ドレイン電極１１に流れる。一方ホール電流
■、は、ドレイン電極ＩＩからＰ゛基板１．ｎ”層２．
ｎ−層３゜２層４からソース電極ｌＯへ流れるが、ｎ−
ＧａＡｓ層６と２層４とのＰ−ｎへテロ接合部分ではブ
ロックされる。この段階で寄生サイリスク構造が作られ
るが、ヘテロ接合により、ホールに対する障壁は、５ｉ
−５ｔのホモ接合を使った従来のものより、０．３ｅＶ
程高くなる。しかして、ソース電極１０．ｎ−ＧａＡｓ
層６．Ｐ−Ｓ３層４．ｎ−５ｉ層３の結合のエネルギー
状態は第２図のようになり、電子ｅは障壁イを越えて流
れる。一方ホールｈは障壁口を越えてソース電極１０側
へ流れる。Since the field effect transistor of the present invention is configured in this way, the electron current 1. , from the n-GaAs layer 6 to the gate electrode 9. Injected into the n-channel 4' formed by the gate oxide film 8 and the two layers 4, the n'' layer 3.n° layer 2.P
0 board 1. The current flows to the drain electrode 11. On the other hand, the Hall current (2) is from the drain electrode II to the P'substrate 1. n” layer 2.
It flows from the n- layer 3゜2 layer 4 to the source electrode lO, but the n-
It is blocked at the Pn heterojunction between the GaAs layer 6 and the second layer 4. At this stage, a parasitic silicon structure is created, but due to the heterojunction, the barrier to holes is 5i
-0.3 eV compared to the conventional one using a homojunction of -5t
moderately high. Therefore, the source electrode 10. n-GaAs
Layer 6. P-S3 layer 4. The energy state of the bond in the n-5i layer 3 is as shown in FIG. 2, and electrons e flow across the barrier a. On the other hand, the holes h flow to the source electrode 10 side beyond the barrier port.
寄生サイリスタのラッチアップ防止には、障壁口の高い
方が有利であるが、従来のように５ｉＳｉのホモ接合を
使う限り、伝導帯と価電子帯との幅は１．１２ｅＶであ
り、障壁１９口は同じ高さしか持たない。これに対して
本発明のようにＧａＡｓのへテロ接合を用いると、Ｇａ
ＡｓがＳｔに比して大きな禁制帯を持つために、障壁口
はイに比べて０．３ｅＶ程高くなり、ホールに対するブ
ロック効果が大きくなる。一般に障壁口における最低許
容電位差は、０．６〜０．７ｅＶまでと云われているか
ら、０．３ｅＶのブロック効果の寄与は大きい。従って
、最終的にホールは２層４からＰ゛層５通ってソース電
極１０へ抜ける。なお、ｎ−ＧａＡｓエピタキシャル層
６はＭ ｉ（Ｉ’：（Ｍｏ１２ ｅｃｕ１２ ａｒ
Ｂｅａｍ ｒａｐ ｉ ｆ ａｘ １ａＣ）法等により
形成する。In order to prevent parasitic thyristor latch-up, it is advantageous to have a higher barrier opening, but as long as a 5iSi homojunction is used as in the past, the width between the conduction band and the valence band is 1.12 eV, and the barrier 19 The mouths should only be at the same height. On the other hand, when a GaAs heterojunction is used as in the present invention, GaAs
Since As has a larger forbidden band than St, the barrier opening is about 0.3 eV higher than that of A, which increases the blocking effect against holes. Generally, the minimum allowable potential difference at the barrier port is said to be 0.6 to 0.7 eV, so the contribution of the blocking effect of 0.3 eV is large. Therefore, the holes finally escape from the second layer 4 through the P' layer 5 to the source electrode 10. Note that the n-GaAs epitaxial layer 6 has M i (I': (Mo12 ecu12 ar
It is formed by a beam rap i f ax 1aC) method or the like.
−１−記実施例はＰ層をエピタキシャル層としているが
拡散層としてもよい。-1- In the embodiment described above, the P layer is an epitaxial layer, but it may also be a diffusion layer.
１−１ 、発明の効果
本発明は、上述のとおり構成されているので、寄生サイ
リスタのラブチアツブ現象の起こる電圧を大ｉＪに高く
することができる。1-1. Effects of the Invention Since the present invention is configured as described above, it is possible to increase the voltage at which the love-throttle phenomenon of the parasitic thyristor occurs to a large iJ.
第１図は本発明の実施例を示す要部正断面図、第２図（
改）、（ｂ）は接合部のエネルギー状態説明図、第３図
はラブチアツブ現象の起こる電圧曲線図、第４図乃至第
６図は夫々異なる従来電界効果トランジスタを示す要部
正断面図、第７図は寄生サイリスクの構成図、第８図（
ａ）は電子及びホールの経路説明図、第８図（ｂ）は経
路抵抗外２名
第３図
第５図
第４図
第６図
第７図
第８図Figure 1 is a front sectional view of the main part showing an embodiment of the present invention, Figure 2 (
(revised), (b) is an explanatory diagram of the energy state of the junction, Figure 3 is a voltage curve diagram where the love-bubble phenomenon occurs, Figures 4 to 6 are front cross-sectional views of main parts showing different conventional field effect transistors, respectively. Figure 7 is a diagram of the structure of a parasitic rhinoceros risk, and Figure 8 (
a) is an explanatory diagram of the paths of electrons and holes, and Fig. 8 (b) is an illustration of the path resistance for two people. Fig. 3 Fig. 5 Fig. 4 Fig. 6 Fig. 7 Fig. 8
Claims (1)
ース層から前記Ｐ層にかけてソース電極を接合してなる
堅型バイポーラＭＯＳＦＥＴ又は堅型バイポーラＶＭＯ
ＳＦＥＴにおいて、 前記ｎ＾＋ソース層を、ｎ＾＋−ＧａＳｉエピタキシャ
ル層とすると共に、前記Ｐ層の反転層より離れた位置の
上部にＰ＾＋拡散層を設け、前記ソース電極を前記ｎ＾
＋−ＧａＡｓエピタキシャル層及びＰ＾＋拡散上に接合
してなることを特徴とする電界効果トランジスタ。(1) A hard bipolar MOSFET or a hard bipolar VMO in which an n^+ source layer is provided above the P layer and a source electrode is connected from this n^+ source layer to the P layer.
In the SFET, the n^+ source layer is an n^+-GaSi epitaxial layer, a P^+ diffusion layer is provided above a position away from the inversion layer of the P layer, and the source electrode is formed as the n^+ GaSi epitaxial layer.
A field effect transistor characterized in that it is bonded to a +-GaAs epitaxial layer and a P^+ diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP408589A JPH02184078A (en) | 1989-01-11 | 1989-01-11 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP408589A JPH02184078A (en) | 1989-01-11 | 1989-01-11 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02184078A true JPH02184078A (en) | 1990-07-18 |
Family
ID=11574949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP408589A Pending JPH02184078A (en) | 1989-01-11 | 1989-01-11 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02184078A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000010204A1 (en) * | 1998-08-14 | 2000-02-24 | Koninklijke Philips Electronics N.V. | Trench-gate semiconductor device |
| RU2472248C2 (en) * | 2010-03-03 | 2013-01-10 | Общество с ограниченной ответственностью "Интелсоб" (ООО "Интелсоб") | High-voltage high-temperature quick-acting thyristor with field control |
| JP2013034031A (en) * | 2012-11-20 | 2013-02-14 | Nissan Motor Co Ltd | Semiconductor device and manufacturing method of the same |
| CN110752254A (en) * | 2019-10-25 | 2020-02-04 | 上海华力集成电路制造有限公司 | Stress channel transistor and manufacturing method thereof |
-
1989
- 1989-01-11 JP JP408589A patent/JPH02184078A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000010204A1 (en) * | 1998-08-14 | 2000-02-24 | Koninklijke Philips Electronics N.V. | Trench-gate semiconductor device |
| US6255692B1 (en) | 1998-08-14 | 2001-07-03 | U.S. Philips Corporation | Trench-gate semiconductor device |
| RU2472248C2 (en) * | 2010-03-03 | 2013-01-10 | Общество с ограниченной ответственностью "Интелсоб" (ООО "Интелсоб") | High-voltage high-temperature quick-acting thyristor with field control |
| JP2013034031A (en) * | 2012-11-20 | 2013-02-14 | Nissan Motor Co Ltd | Semiconductor device and manufacturing method of the same |
| CN110752254A (en) * | 2019-10-25 | 2020-02-04 | 上海华力集成电路制造有限公司 | Stress channel transistor and manufacturing method thereof |
| CN110752254B (en) * | 2019-10-25 | 2023-09-19 | 上海华力集成电路制造有限公司 | Stress channel transistor and manufacturing method thereof |
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