JPH0494575A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a decrease in breakdown strength of a MIS type field- effect transistor by forming a gate electrode in a step of a substrate semiconductor substrate and a drain region on the upper stage of the step, and forming an L-shaped channel region over a sidewall from the bottom of the step. CONSTITUTION:A recess step 25 is formed on a thin silicon film 23 of an SOI substrate 24, and a gate electrode 27 is formed in the recess through a gate insulating film 26. Then, n-type source region 28 and drain region 29 are so formed on regions of upper stages of both steps for holding the electrode 27 that boundaries 28a, 29a of a channel region 301 are disposed above at the same distance (d) from the bottoms of the recesses 25, thereby forming a MIS type field-effect transistor (MIS FET) having a U-shaped channel region 301. A drain current Id directed from the region 28 to the region 29 is reduced at the current flowing through a high electric field A under the gate electrode. Thus, a decrease in breakdown strength due to impact ionization can be suppressed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a so-called S○I (semiconductor on 1n) in which a semiconductor thin film is formed on an insulating substrate.
The present invention relates to a MIS type semiconductor device in which a semiconductor element with an MIS structure is formed using a sulatar substrate.

[Summary of the invention]

The present invention provides an MIS type semiconductor device in which a gate electrode is formed within a step formed in a semiconductor layer on an insulating substrate via a gate insulating film, and at least a drain region is formed above the step. By configuring the interface between the drain region and the channel region to exist above the bottom surface of the stepped portion, a decrease in breakdown voltage due to impact ionization, which is a drawback of MIS semiconductor devices formed on SOI substrates, can be suppressed, and this type of This is intended to improve the reliability of the MIS type semiconductor device.

The present invention also provides an MIS type semiconductor device in which a gate electrode is formed within a step formed in a semiconductor layer on an insulating substrate via a gate insulating film, a drain region is formed above the step, and a drain region is formed on the bottom of the step. By forming and configuring an L-shaped channel region extending from the sidewall to the sidewall, a decrease in breakdown voltage due to impact ionization, which is a drawback of MIS type semiconductor devices formed on an SOI substrate, can be suppressed, and further,
This type of M I S
This is intended to improve the reliability of the type semiconductor device.

2.Recently, MIS field effect transistors (hereinafter referred to as SFETs) using SOI substrates are capable of high speed operation due to high alpha ray resistance and reduced latch-up IJ-1 parasitic capacitance. Because it has the advantages of
Development is actively underway.

this! , IIs FET usually has an island-shaped silicon thin film (
2) is used, and this silicon thin film (2) is provided with a source region and a drain region of the first conductivity type, in the example shown, high concentration regions (4a), (5a) and low concentration regions ( 4b), the so-called L having (5b)
An n-type source region (4) and a drain region (5) having a D D (lightly doped drain) structure are formed, and an Si port 2, for example, is formed on the silicon thin film (2) between the source region (4) and the drain region (5). A gate electrode (7) made of, for example, polycrystalline silicon is formed through a gate insulating film (6) such as the like. (8) is the source electrode, (
9) is a drain electrode.

[Problem to be solved by the invention 2 However, it is difficult to solve the problem by using SOI substrate (3).
In the FET (10), the source-drain breakdown voltage in the OFF state, that is, the source-drain breakdown voltage is low, 1
There are some drawbacks. As shown in FIG. 7, in the old 5FET (10), if the gate voltage Vg≦threshold voltage Vth, the electric field at the drain end under the gate electrode (7) becomes considerably high, so the source region (4) Chiaria (electrons) e injected into the channel region (11) flow toward the drain region (5), and these electrons (e) cause impact ionization in the high electric field region (12) at the end of the drain. , caused by the generation of electron-hole pairs, of which holes (h) flow into the channel region (11). In other words, the normal Nork-type old S
In the FET, holes h (so-called hole current IP) flowing into the channel escape as substrate current through the substrate, but in this SO substrate (3), the silicon thin film (3)
Since the structure is such that the holes are surrounded by 102 layers (1) and cannot escape, the holes accumulate in the channel region (11) near the source region (4). The accumulated holes lower the energy barrier between the source and the chianel, and as a result, the source region acts as an electron emitter and the normal flow of electrons (chianel current flow) into the channel region (11). In addition, the bipolar-operated electron current A is generated. This electron current I. again causes a positive feedback phenomenon in which a hole current I is generated in the high electric field region (12), causing a rapid increase in the drain current, resulting in a decrease in the source-drain breakdown voltage. That is, 1 in FIG. -V, as shown in the curve diagram, at a high gate voltage V, l, the source-drain breakdown voltage becomes as shown in curve (I), and there is no problem with the source-drain breakdown voltage, but at a low gate voltage, V, 2, as shown in curve (I[), The source-drain breakdown voltage decreases.

Attempts to suppress this drop in breakdown voltage by lowering the concentration in the low concentration region of the LDD structure have not been successful so far. The simulation results show that it is impossible to deal with the problem using LDD.

In view of the above-mentioned points, the present invention provides an MIS type semiconductor device which can suppress a drop in breakdown voltage due to impact ionization and improve the reliability of the semiconductor device itself.

[Means to solve the problem]

The MIS type semiconductor device according to the present invention has an insulating substrate (22
) a semiconductor layer (23) is formed on the semiconductor layer (23);
) A gate insulating film (26) is formed within the stepped portion (25) formed in the
A gate electrode (27) is formed through the step, and at least a drain region (29) is formed in the upper step of the stepped portion.
29) and the channel region (30,) interface (29a
) is located above the bottom of the stepped portion.

The source region (28) may be formed at the top of the other step facing the drain region (29) (the channel region is U-shaped), or it may be formed at the bottom of the step (the channel region is U-shaped). is L-shaped).

Further, in the MTS type semiconductor device according to the present invention, a semiconductor layer (23) is formed on an insulating substrate (22), and a gate insulating film (
26), a drain region (29) is formed on the upper level of the stepped portion, and an L-shaped channel region (302) extending from the bottom of the stepped portion (33) to the sidewalls is formed.
form and compose.

[Effect]

According to the first aspect of the invention, the gate electrode (27) is formed within the step portion (25) of the semiconductor layer (23) via the gate insulating film (26), and at least the drain region (29) is formed within the step portion (25). The interface (29a) between the drain region (29) and the channel region (30,) is formed above the bottom surface of the step part, so that the channel region (30,) is formed at the upper level of the drain region (29,). ) side is bent along the step side wall. Therefore, the source area (28
) toward the drain region (29) avoids the region (A) near the drain end under the gate electrode where the electric field is strongest. As a result, the impact
Ionization is significantly reduced and source-drain breakdown voltage is improved.

According to the second aspect of the invention, the step portion (3) of the semiconductor layer (23)
3) A gate electrode (2
By forming the drain region (29) in the upper step of the step part and forming the chianel region (302) in an L shape extending over the bottom side wall of the step part (33), the drain region (29) can be formed in the same way. The current flow avoids the region (A) where the electric field is strongest near the drain end under the gate electrode, thereby significantly reducing impact ionization and improving the source-drain breakdown voltage. In addition, by forming the source region (28) below the step to form an L-shaped channel region (302), the resistance near the source is reduced, the saturation current I is further increased, and the distance between the source region and the drain is reduced. The current path length between the regions can also be reduced.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

In addition, in each example, n channel! , is applied to an IIS FET, but it can also be applied to a p-channel MIS FET.

FIG. 1 shows an example of the invention. In this example, a 501 substrate (24) is used, which is formed by forming, for example, a silicon thin film (23) isolated in an island shape on a silicon substrate (21) via an 810□ layer (22). This SOI substrate (2
4) silicon thin film, that is, a p-type silicon thin film (
A step portion or trench (25) is formed in the second groove (25), and a gate electrode (25) made of, for example, polycrystalline silicon is formed in the second groove (25) via a gate insulating film (26) made of, for example, SlO□. 27). And the concave groove (25
), an n-type source region (28) and a drain region (29) are formed in the silicon thin film regions on both sides of the gate electrode (27) (ie, the upper region of both step portions). At this time, at least the drain region (29) is connected to the channel region (
30,) so that the interface (29a) with the groove (29a) is located above the bottom surface of the groove (25) by a required distance d. In this example, a source region (28) and a drain region (28) are used.
9) at the interface (28') with the channel region (30,)
a) and (29a) are respectively formed above the bottom surface of the concave groove (25) by the same distance d, and the so-called U
It forms a letter-shaped chianel region (30,). The film thickness t under the groove (25) in which the gate electrode (27) is formed is an extremely thin film of about 500 layers. In this way, the MIS FE comprising the U-shaped channel region (30,)
Configure T(32).

(S), (G), and (D) are a source terminal, a gate terminal, and a drain terminal, respectively.

Figure 2 takes a while! , IIs FET (32).

As shown in FIG. 2, a Sol substrate ( 2
4) Prepare.

Next, as shown in Figure 2, a groove (25) for burying the gate electrode is formed by leaving a film thickness t in the silicon thin film (23), and then gate oxidation is performed to form the groove (25). groove(
25) Form a gate insulating film (26) on the inner surface.

Next, as shown in FIG. 2C, a polycrystalline silicon film is formed including the inside of the groove (25), and etched back to form a gate electrode (27) made of polycrystalline silicon in the groove (25).
) to form. Next, n-type impurities are ion-implanted to form n-type source regions (28) and drain regions (29) in the silicon thin film regions on both sides of the trench (25) so as to be shallower by a distance d from the bottom surface of the trench. As a result, an old 5FET (32) having the desired U-shaped channel region (30,) is obtained.

According to the old SFET (32) having such a configuration, since the channel region (30,) is formed in a U-shape, the drain current flowing from the source region (28) to the drain region (29) is 1. The flow avoids the region (A) where the electric field is strongest near the drain region (29).

That is, the current flowing through this high electric field region (A) decreases. Impact ionization is proportional to drain current 1d, and for electric field E, exp (--)
(However, α is a constant), so the old S FET
(32), impact ionization is significantly reduced and source-drain breakdown voltage is improved.

Fig. 5 shows an n-chi = jr-ru! using a Mis FET (32) and a normal SOI substrate shown in Fig. 7. , 11S
The characteristics of the FET (hereinafter referred to as 5OI-n!JIS FET), that is, the gate voltage V, 1°-V below the threshold voltage Vth (that is, before the formation of the inversion layer) are shown. Curve (lI
[) Li old S FET (32) (7) Characteristics, curve (
IV) is the normal 5OI-n! , which are the characteristics of IIS FET. As is clear from this characteristic diagram, the normal 5OI
-n In the MIS FET, the gate closes poorly when the drain voltage Vd=3V, but in the MIS FET (32), the gate closes well even when the drain voltage Vd=5V.
, <1 at Vth. -V, the characteristics are improved and the source-drain breakdown voltage is improved.

In addition, the thickness t of the silicon thin film under the gate electrode (27),
As the thickness is reduced to about 500, the short channel effect becomes less likely to occur, and the amount of electrons not controlled by the gate voltage decreases, resulting in improved characteristics.

Therefore, in the old S FET (32) of this example,
By suppressing the breakdown voltage drop due to impact ionization without sacrificing the advantages of MIS type semiconductor devices formed using S○■ substrates, this type of MIS
The reliability of the S-type semiconductor device itself can be improved.

In FIG. 1, it is also possible to form the source region (28) to cover the entire thickness of the silicon thin film (23) and configure the chianel region to be U-shaped.

FIG. 3 shows another example of the invention. In this example, an SOI substrate (24) is used, which is formed by forming a silicon thin film (23) isolated in an island shape on a silicon substrate (21) via an 8102 layer (22), as in the case above. ■ Grooves (33) in the p-type silicon thin film (23) of the substrate (24)
) to form a stepped portion, and a gate electrode made of, for example, polycrystalline silicon is formed on one side of the groove (33) through a gate insulating film (26) made of, for example, 5i02, covering the bottom and side walls. (27) is formed. The thickness t of the silicon thin film (23) under the groove (33) is an extremely thin film of about 500 layers. Then, an n-type drain region (29) is formed in the silicon thin film region of the side wall (i.e., the upper region of the stepped portion), and the interface (29a) with the channel region (30□) is the concave groove (33).
) above the bottom surface of the drain region (29) with the gate electrode (27) in between.
) at the bottom of the groove (33) facing the silicon thin film region (
In other words, an n-type source region (28) is formed in the region below the step, and a so-called letter-shaped chianel region (3G2) is formed! , (Is FET (34)).

FIG. 4 shows an example of a manufacturing method for such old S 5ET (34>).

As shown in FIG. 3A, a Sol substrate (2
4) is prepared, and an n-type impurity such as phosphorus (P) (35) is ion-implanted into the silicon thin film (23) of this 5C1r substrate (24) to form an n' region 2 for forming a drain region.
9. ) to form.

Next, as shown in Fig. 4, one part of the silicon thin film (23) is
A trench (33) is formed in half, and a trench (3) is formed in the half.
3) thermally oxidize the inner surface to form a gate insulating film (26). The remaining n-region (23) of the other half of the silicon thin film (23)
29,) becomes an n-type drain region (29). The groove (33) is configured to be deeper than the drain region (29) by a required distance d, leaving a bottom film thickness t of about 500 Å.

Next, as shown in FIG. 4C, a polycrystalline silicon film (27,) is deposited by CVD (chemical vapor deposition) so as to fill the groove (33), and an etch hack is performed. Polycrystalline silicon film (27,) only in the groove (33)
form.

Next; Second, a part of the polycrystalline Nurico/membrane (27,), i.e.
Two polycrystalline silicon films are left in contact with the side wall of the groove (33) on the side of the drain region (29) and a part of the bottom surface continuous thereto via the gate insulating film (26), and the other parts are removed by etching. , here a gate electrode made of polycrystalline silicon <2
7). Thereafter, a source region (28) is formed by selectively ion-implanting n-type impurities into the silicon thin film region where the polycrystalline silicon film has been removed.
Old S having a U-shaped channel region (302)
Obtain FET (34).

According to the Mis FET (34) having such a configuration, the source region (28) is formed at the bottom of the step, the toluin region (29) is formed at the top of the step, and the chianel region (28) is formed at the top of the step.
302) is formed in an L-shape along the step, so that the drain current flows from the source region (28) to the drain region (29) as in FIG. flows to avoid the region A near the drain region where the electric field is strongest, and the current flowing through this high electric field region (A) becomes smaller.
The generation rate of minority carriers due to impact ionization is significantly reduced, the I, -V characteristics show the same tendency as the curve (II[) in FIG. 5, and the source-drain breakdown voltage is improved. On the other hand, the aforementioned U-shaped channel region (
30+) tits FET (32)
Li, gate voltage v9 is below VthEJ, -v,
Although the improvement of characteristics and breakdown characteristics is delayed, 5C1l-n of normal LDD structure! , IIs FET, the saturation current (2) is small, and the current path length between the source region and the drain region is large. However, the old S FET (34) in the embodiment of FIG.
30,) is formed in an L shape, so the first U
MIS FET (3) with shape channel region (30,)
2) The source resistance is reduced and the saturation current is reduced compared to 1. increases, and the current path length (in FIG. 3, the same as the effective channel length since it does not have an LDD structure) also decreases. MISFE
T(34) allows the current path length to be designed to be the same as that of a 5Of-n MIS FET with a normal LDD structure. Figure 6 shows the normal 5ol-n
MISPET, MISFET (32) with U-shaped channel region (30□), and MIS FET (34) with L-shaped channel region (302)
(!: Compare i: V, = vth -2,7v I, -V, curve (V) showing the characteristics is 5Of-n
Old 5FETO characteristics, the curve (Vl) has a U-shaped channel area! , the characteristics of IS FET (34), the curve (■) shows the characteristics of Mis FET (
32). Old S with U-shaped channel area
The FET (32) has a large breakdown voltage (high breakdown voltage) but a small saturation voltage I. However, the U-shaped channel region MIS FET (34) has a saturation current I
, is comparable to that of a normal S[]rn MISFET, and the breakdown voltage is significantly larger.

Therefore, in the old S FET (34), SOI
Without sacrificing the advantages of using a substrate, it is possible to suppress the drop in breakdown voltage due to impact and ionization, and the reliability of the MIS type semiconductor device itself can be improved. The saturation current, current path length, etc. can be improved compared to the conventional method.

Effects of the invention: According to the invention, M formed using an SOi substrate
Without impairing the advantages of the IS type semiconductor device, a decrease in breakdown voltage due to impact ionization can be suppressed, and the reliability of the MIS type semiconductor device itself can be improved. Furthermore, when forming a U-shaped channel region, the saturation current characteristics can be further improved and the current path length between the source region and the drain region can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an example of a MrS type semiconductor device according to the present invention, and FIGS. 2A to 2C are manufacturing process diagrams showing an example of its manufacturing method.
FIG. 3 is a configuration diagram showing the other side of the MIS type semiconductor device according to the present invention, and FIGS. 4A to 4D are manufacturing process diagrams showing an example of its manufacturing method.
Figure 5 is an r, -V, characteristic diagram used to explain the present invention, and Figure 6 is a
The figures are r, -V and characteristic diagrams for explaining the present invention, FIG. 7 is a configuration diagram of a general old 5FET, and FIG. 8 is an IdVd characteristic diagram for explaining the conventional technology. (21) is a silicon substrate, (22) is a SlO□ layer, (2
3) is a silicon thin film, (24) is an S○■ substrate, (25)
is a groove, (26) is a gate insulating film, (27) is a gate electrode, (28) is a source region, (29) is a drain region,
(30,) is a U-shaped chianel region, and (30□) is a U-shaped chianel region.
This is the glyph chianel region. Agent Hidemori Matsukuma 2F--・Silicon-filled anti-22--5iOz layer 23-...Silicon thin film z4---SOI base resin δ゛...--Concave 26---・--ke °-Tojiji change〕Evening 27・--・Kate distribution 2B--Source control board 2q---1 drain @ rice 301- ・-U-shaped channel @toen 32・---M
ISFET 1st direction 1 dz Fig. 1 d -Vq characteristic diagram Fig. 5 Manufacturing process opening Fig. 2 23-・-・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ＧＧＧＧcus/SW. --... Torrein 舊iya 33-・-m- and L amount 302- ・-inverted type channel → iron 74-・-・-MISFET 2nd Jitsuri no Karisenki 3rd figure V9: Vth+ 2.7 V d Id - Vd characteristic opening Figure 6 Figure 4 Oval diagram of a typical MISFET Figure 7 -L, A 2 electric solenoid 3 Vd Id - Vd Special A forward curve Latitude circle Figure 8

Claims (1)

[Claims] 1. A semiconductor layer is formed on an insulating substrate, a gate electrode is formed within a step formed in the semiconductor layer via a gate insulating film, and at least a drain region is formed above the step. An MIS type semiconductor device in which the interface between the drain region and the channel region is located above the bottom surface of the stepped portion. 2. A semiconductor layer is formed on an insulating substrate, a gate electrode is formed within a step formed in the semiconductor layer via a gate insulating film, and a drain region is formed above the step and extends from the bottom of the step. M formed with an L-shaped channel region extending over the sidewalls.
IS type semiconductor device.