JPS638507B2 - - Google Patents

Info

Publication number
JPS638507B2
JPS638507B2 JP19332782A JP19332782A JPS638507B2 JP S638507 B2 JPS638507 B2 JP S638507B2 JP 19332782 A JP19332782 A JP 19332782A JP 19332782 A JP19332782 A JP 19332782A JP S638507 B2 JPS638507 B2 JP S638507B2
Authority
JP
Japan
Prior art keywords
computer
stop
interrupt
command
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19332782A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5983262A (ja
Inventor
Hiroshi Watanabe
Ryoichi Takamatsu
Yoshihiro Myazaki
Keijiro Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19332782A priority Critical patent/JPS5983262A/ja
Publication of JPS5983262A publication Critical patent/JPS5983262A/ja
Publication of JPS638507B2 publication Critical patent/JPS638507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP19332782A 1982-11-05 1982-11-05 マルチコンピユ−タシステムにおけるコンピユ−タ停止装置 Granted JPS5983262A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19332782A JPS5983262A (ja) 1982-11-05 1982-11-05 マルチコンピユ−タシステムにおけるコンピユ−タ停止装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19332782A JPS5983262A (ja) 1982-11-05 1982-11-05 マルチコンピユ−タシステムにおけるコンピユ−タ停止装置

Publications (2)

Publication Number Publication Date
JPS5983262A JPS5983262A (ja) 1984-05-14
JPS638507B2 true JPS638507B2 (enrdf_load_stackoverflow) 1988-02-23

Family

ID=16306052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19332782A Granted JPS5983262A (ja) 1982-11-05 1982-11-05 マルチコンピユ−タシステムにおけるコンピユ−タ停止装置

Country Status (1)

Country Link
JP (1) JPS5983262A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS5983262A (ja) 1984-05-14

Similar Documents

Publication Publication Date Title
US6026455A (en) Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system
JPS63175962A (ja) 直接メモリアクセス制御装置とマルチマイクロコンピュータシステム内におけるデータ転送方法
JPS638507B2 (enrdf_load_stackoverflow)
JPH05289987A (ja) バス権調停回路
JPS624746B2 (enrdf_load_stackoverflow)
JPS629418A (ja) タイマ制御方式
JPS58165164A (ja) 情報源管理方式
JP2531080B2 (ja) バスアダプタ切り換え方式
JPS5845050B2 (ja) バス集中監視方式
JPS595331A (ja) 磁気デイスク・サブシステムにおける待ち合せ方式
JPH0216667A (ja) プロセッサ・システム
JPS597971B2 (ja) 入出力装置の制御方式
JPS6029856A (ja) マルチプロセツサ・システムにおけるロ−カルメモリのアクセス制御方式
JPH0533414B2 (enrdf_load_stackoverflow)
JPS63155351A (ja) マルチプロセツサシステム
JPH0511339B2 (enrdf_load_stackoverflow)
JPH01211152A (ja) バス転送制御方式
JPH06266630A (ja) トレース機能付き入出力制御装置
JPH02144653A (ja) データ処理装置
JPS58121468A (ja) マルチプロセツサ装置
JPS63310035A (ja) マイクロコンピユ−タ
JPH0520250A (ja) データ処理装置
JPH06208541A (ja) マルチタスクシステムにおけるバス制御装置
JP2000076182A (ja) バス調停方式
JPS62219059A (ja) マルチｃｐｕ形コンピユ−タ−における共通メモリ−のアクセス権制御回路