JPS636848A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS636848A
JPS636848A JP61149423A JP14942386A JPS636848A JP S636848 A JPS636848 A JP S636848A JP 61149423 A JP61149423 A JP 61149423A JP 14942386 A JP14942386 A JP 14942386A JP S636848 A JPS636848 A JP S636848A
Authority
JP
Japan
Prior art keywords
glass
paste
glass paste
die
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61149423A
Other languages
English (en)
Inventor
Keigo Nakatani
圭吾 中谷
Isato Usami
宇佐美　勇人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61149423A priority Critical patent/JPS636848A/ja
Publication of JPS636848A publication Critical patent/JPS636848A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
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    • H01L2224/29199—Material of the matrix
    • H01L2224/29286—Material of the matrix with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29288—Glasses, e.g. amorphous oxides, nitrides or fluorides
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    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/29339—Silver [Ag] as principal constituent
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要〕 ガラスペーストをダイステージに焼結し、銀（Ａｇ）ガ
ラスペーストで半導体ｉｆ回路チップをダイス付けする
。
〔産業上の利用分野〕
本発明は半導体装置に関するもので、さらに詳しく言え
ば、集積回路が形成された半導体チップがパッケージの
ステージ上の焼結したガラス層上にダイス付けされてな
る半導体集積回路パッケージに関するものである。
〔従来の技術〕
集積回路が形成された半導体チ・ノブ（以下には単にＩ
Ｃチップという）がステージ上にダイス付けされてなる
セラミックパッケージは知られたもので、それは第２図
の断面図に示される構造のものである。第２図において
、１１はセラミックのグリンシートを積層し焼結して作
られたセラミックのパッケージ本体、１２はその上にＩ
Ｃチップ１３がダイス付けされるダイステージ、１４は
ＩＣチップ１３の電極とパッケージ本体に形成されたイ
ンナーリード１５とを接続するワイヤ（ワイヤ１４はワ
イヤボンディングによって接続される）、１６はインナ
ーリードに接続された外リードである。ＩＣチップ１３
はステージ１２上にグイボンディングでダイス付けされ
る。
ＩＣチップ１３のダイス付けには従来例えば金ペースト
を用いるＡｕＳｉダイス付は方法が用いられたが、金ペ
ーストは高価であるため、それに代えてＡｇガラスペー
ストを用いる方法が提案された。その方法を第２図を参
照して説明すると、ダイステージ１２上にＡｇガラスペ
ースト１７を塗布し、その上にＩＣチップ１３を自動的
なグイボンディング法でダイス付けし、しかる後に３５
０℃〜４００℃の熱でキュア（ｃｕｒｅ）　Ｌ、てＡｇ
ペーストを硬化させＩＣチップ１２を接着する。
〔発明が解決しようとする問題点〕
ＡｕＳｉＡｕＳｉダイス付ガラスペーストを用いる理由
は、それが金ペーストに比べてコストが安いだけでなく
、Ａｇガラスペーストのガラス（５ｉ０２）の酸素と、
セラミック（ＡｘＬｏ３）の酸素とのマツチングによっ
てＩＣチップとＡｇガラスペーストとの結合が得られる
からである。しかし、Ａｇガラスダイス付けの強度はＡ
ｕＳｉダイス付けの強度より劣っている。
本発明はこのような点に鑑みて創作されたもので、Ａｇ
ガラスペーストを用いるＩＣチップのダイス付けにおい
て、接着強度が更に高められた半導体ＩＣパッケージを
提供することを目的とする。
〔問題点を解決するための手段〕
第１図は本発明実施例の断面図である。
本発明においては、ダイステージ１２上にガラスペース
トを塗布しそれを焼結してガラス層１８を形成しておき
、その上にＡｇガラスペースト１７を塗布し、次いでＩ
Ｃチップ１３をダイス付けし、Ａｇガラスペースト１７
をキュアして半導体ＩＣパッケージを形成する。
〔作用〕
前記したパッケージにおいては、Ａｇガラスペースト中
のガラスと焼結したガラスとが溶は合い、ガラスとガラ
スのマツチング（結合）が得られるので、十分に高い強
度の結合が得られるのである。
〔実施例〕
以下、図面を参照して本発明の実施例を詳細に説明する
。
再び第１図を参照すると、パッケージ本体１１およびイ
ンナーリード１５、外リード１６などは従来例と同様に
形成されるものである。
パッケージ本体のダイステージ１２上には融点４００°
Ｃ近傍のガラスペーストを塗布し、焼結することによっ
て、例えば数μｍぐらいの厚さに焼結したガラス層１８
が形成されている。
ガラス層１８の上にはＡｇガラスペースト１７を塗布し
その上にＩＣチップ１３をグイボンディング法によって
ダイス付けする。次いで、従来例同様３５０℃〜４００
℃の温度でＡｇガラスペーストをキュアし、Ａｇガラス
ペーストのガラスとガラス層１８とが溶は合うようにす
る。このガラスとガラスのマツチング（結合）によって
Ａｇガラスペースト１７とガラス１’ｉ＃１８とは強固
に結合し、ＡｕＳｉと同等の強度が得られた。
次いで、ワイヤボンディングによってＩＣチップ１３の
電極１３ａ・とパッケージのインナーリード１５とを接
続し、しかる後にキャップ１９を封止して半導体パッケ
ージを完成する。
〔発明の効果〕
以上述べてきたように本発明によれば、半導体ＩＣパッ
ケージにおいてＩＣチップはパッケージのダイステージ
に強固にダイス付けされ、しかもそのコストは従来例に
比べ低減される効果がある。
【図面の簡単な説明】
第１図は本発明実施例の断面図、 第２図は従来例の断面図である。 第１図と第２図において、 １１はパッケージ本体、 １２はダイステージ、 １３はＩＣチップ、 １３ａはＩＣチップ１３の電極、 １４はワイヤ、 １５はインナーリード、 １６は外リード、 １７はＡｇガラスペースト、 １８は焼結したガラス層、 １９はキャップである。 代理人　　弁理士　　久木元　　　彰 復代理人　弁理士　　大　菅　義　之 しト、列間ト８８莢）１！イテリｄプｒｄジ５フ第１９ 彼米例絣の口 第２□□□

Claims (1)

  1. 【特許請求の範囲】 パッケージ本体（１１）のダイステージ（１２）上には
    ガラスペーストを焼結してなるガラス層（１８）が設け
    られ、 ガラス層（１８）の上に塗布された銀ガラスペースト（
    １７）上には集積回路が形成された半導体チップ（１３
    ）がダイステージ付けされ、銀ガラスペーストは熱硬化
    （キュア）されてなることを特徴とする半導体装置。
JP61149423A 1986-06-27 1986-06-27 半導体装置 Pending JPS636848A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61149423A JPS636848A (ja) 1986-06-27 1986-06-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61149423A JPS636848A (ja) 1986-06-27 1986-06-27 半導体装置

Publications (1)

Publication Number Publication Date
JPS636848A true JPS636848A (ja) 1988-01-12

Family

ID=15474785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61149423A Pending JPS636848A (ja) 1986-06-27 1986-06-27 半導体装置

Country Status (1)

Country Link
JP (1) JPS636848A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618540B1 (ko) * 1999-06-17 2006-08-31 삼성전자주식회사 금속덮개 봉지형 반도체 칩 패키지 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618540B1 (ko) * 1999-06-17 2006-08-31 삼성전자주식회사 금속덮개 봉지형 반도체 칩 패키지 제조 방법

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