JPS6353940A - 半導体装置の自動ワイヤボンデイング方法 - Google Patents

半導体装置の自動ワイヤボンデイング方法

Info

Publication number
JPS6353940A
JPS6353940A JP19759386A JP19759386A JPS6353940A JP S6353940 A JPS6353940 A JP S6353940A JP 19759386 A JP19759386 A JP 19759386A JP 19759386 A JP19759386 A JP 19759386A JP S6353940 A JPS6353940 A JP S6353940A
Authority
JP
Japan
Prior art keywords
bonding
coordinate data
position coordinate
semiconductor element
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19759386A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0477461B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Kiyoaki Tsumura
清昭 津村
Hitoshi Fujimoto
藤本 仁士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19759386A priority Critical patent/JPS6353940A/ja
Publication of JPS6353940A publication Critical patent/JPS6353940A/ja
Publication of JPH0477461B2 publication Critical patent/JPH0477461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
JP19759386A 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法 Granted JPS6353940A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19759386A JPS6353940A (ja) 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19759386A JPS6353940A (ja) 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法

Publications (2)

Publication Number Publication Date
JPS6353940A true JPS6353940A (ja) 1988-03-08
JPH0477461B2 JPH0477461B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-12-08

Family

ID=16377065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19759386A Granted JPS6353940A (ja) 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法

Country Status (1)

Country Link
JP (1) JPS6353940A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPH0477461B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-12-08

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