JPS6352809B2 - - Google Patents

Info

Publication number
JPS6352809B2
JPS6352809B2 JP18256780A JP18256780A JPS6352809B2 JP S6352809 B2 JPS6352809 B2 JP S6352809B2 JP 18256780 A JP18256780 A JP 18256780A JP 18256780 A JP18256780 A JP 18256780A JP S6352809 B2 JPS6352809 B2 JP S6352809B2
Authority
JP
Japan
Prior art keywords
circuit
signal
decoding
dmi
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18256780A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57106222A (en
Inventor
Koji Nishizaki
Masanori Arai
Takemi Endo
Masayuki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP18256780A priority Critical patent/JPS57106222A/ja
Publication of JPS57106222A publication Critical patent/JPS57106222A/ja
Publication of JPS6352809B2 publication Critical patent/JPS6352809B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP18256780A 1980-12-22 1980-12-22 Decoding circuit Granted JPS57106222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18256780A JPS57106222A (en) 1980-12-22 1980-12-22 Decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18256780A JPS57106222A (en) 1980-12-22 1980-12-22 Decoding circuit

Publications (2)

Publication Number Publication Date
JPS57106222A JPS57106222A (en) 1982-07-02
JPS6352809B2 true JPS6352809B2 (US20100223739A1-20100909-C00025.png) 1988-10-20

Family

ID=16120527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18256780A Granted JPS57106222A (en) 1980-12-22 1980-12-22 Decoding circuit

Country Status (1)

Country Link
JP (1) JPS57106222A (US20100223739A1-20100909-C00025.png)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02156732A (ja) * 1988-12-09 1990-06-15 Hitachi Ltd 復調装置

Also Published As

Publication number Publication date
JPS57106222A (en) 1982-07-02

Similar Documents

Publication Publication Date Title
US4027335A (en) DC free encoding for data transmission system
JPH0351335B2 (US20100223739A1-20100909-C00025.png)
IE45458B1 (en) Miller-encoded message decoder
USRE31311E (en) DC Free encoding for data transmission system
JPS61208318A (ja) マンチエスタ符号化データのためのデコーダ
US4325053A (en) Method and a circuit for decoding a C.M.I. encoded binary signal
JPS5828981B2 (ja) Ｃｍｉエンコ−ダ
JPH07131448A (ja) 位相比較回路
JPH036698B2 (US20100223739A1-20100909-C00025.png)
JPS6352809B2 (US20100223739A1-20100909-C00025.png)
JPH01141436A (ja) フレーム同期化方法
JPS63257333A (ja) Ｃｍｉ符号化信号用符号解読装置
JP2508502B2 (ja) 復調回路
JP2572969B2 (ja) スプリツトフエ−ズ符号化回路
JPH0590970A (ja) Ｃｍｉエンコーダ回路
JPH1168861A (ja) 同時双方向送受信方法および同時双方向送受信回路
JPS6016147B2 (ja) パルス伝送方式
JP2606194B2 (ja) デジタル信号の伝送装置
KR900005237B1 (ko) Pwm 코딩/디코딩에 의한 디지탈 데이타 전송회로
KR920001856B1 (ko) 교환기 노드간의 순환 반복 코드 시그날링 검출회로
JP2576526B2 (ja) 入出力信号監視回路
JP3008659B2 (ja) Ｃｍｉ符号信号のクロック抽出回路
JPH0323714Y2 (US20100223739A1-20100909-C00025.png)
JPH0462624B2 (US20100223739A1-20100909-C00025.png)
JPS62230242A (ja) ノンリタ−ンゼロデ−タ受信回路