JPS6337418B2 - - Google Patents
Info
- Publication number
- JPS6337418B2 JPS6337418B2 JP58219094A JP21909483A JPS6337418B2 JP S6337418 B2 JPS6337418 B2 JP S6337418B2 JP 58219094 A JP58219094 A JP 58219094A JP 21909483 A JP21909483 A JP 21909483A JP S6337418 B2 JPS6337418 B2 JP S6337418B2
- Authority
- JP
- Japan
- Prior art keywords
- dma
- bus
- cpu
- controller
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 31
- 238000000034 method Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21909483A JPS60110067A (ja) | 1983-11-21 | 1983-11-21 | 簡易型メモリデ−タ転送装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21909483A JPS60110067A (ja) | 1983-11-21 | 1983-11-21 | 簡易型メモリデ−タ転送装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60110067A JPS60110067A (ja) | 1985-06-15 |
JPS6337418B2 true JPS6337418B2 (fr) | 1988-07-25 |
Family
ID=16730161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21909483A Granted JPS60110067A (ja) | 1983-11-21 | 1983-11-21 | 簡易型メモリデ−タ転送装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60110067A (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6484942A (en) * | 1987-09-25 | 1989-03-30 | Nec Corp | Packet buffer control system |
US7284082B2 (en) * | 2004-08-19 | 2007-10-16 | Lsi Corporation | Controller apparatus and method for improved data transfer |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55150032A (en) * | 1979-05-14 | 1980-11-21 | Fujitsu Ltd | Data transfer system |
JPS564826A (en) * | 1979-06-25 | 1981-01-19 | Matsushita Electric Ind Co Ltd | Electronic computer |
JPS5759220A (en) * | 1980-09-26 | 1982-04-09 | Toshiba Corp | Data transfer system |
-
1983
- 1983-11-21 JP JP21909483A patent/JPS60110067A/ja active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55150032A (en) * | 1979-05-14 | 1980-11-21 | Fujitsu Ltd | Data transfer system |
JPS564826A (en) * | 1979-06-25 | 1981-01-19 | Matsushita Electric Ind Co Ltd | Electronic computer |
JPS5759220A (en) * | 1980-09-26 | 1982-04-09 | Toshiba Corp | Data transfer system |
Also Published As
Publication number | Publication date |
---|---|
JPS60110067A (ja) | 1985-06-15 |
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