JPS6335141B2 - - Google Patents

Info

Publication number
JPS6335141B2
JPS6335141B2 JP55125488A JP12548880A JPS6335141B2 JP S6335141 B2 JPS6335141 B2 JP S6335141B2 JP 55125488 A JP55125488 A JP 55125488A JP 12548880 A JP12548880 A JP 12548880A JP S6335141 B2 JPS6335141 B2 JP S6335141B2
Authority
JP
Japan
Prior art keywords
line
control
activation
adapter
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55125488A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5750152A (en
Inventor
Tetsuo Miura
Toshihiko Hiraide
Masao Aoyama
Kunio Furuya
Shigeru Ogasawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP55125488A priority Critical patent/JPS5750152A/ja
Publication of JPS5750152A publication Critical patent/JPS5750152A/ja
Publication of JPS6335141B2 publication Critical patent/JPS6335141B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
JP55125488A 1980-09-10 1980-09-10 Communication control processor Granted JPS5750152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55125488A JPS5750152A (en) 1980-09-10 1980-09-10 Communication control processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55125488A JPS5750152A (en) 1980-09-10 1980-09-10 Communication control processor

Publications (2)

Publication Number Publication Date
JPS5750152A JPS5750152A (en) 1982-03-24
JPS6335141B2 true JPS6335141B2 (enrdf_load_stackoverflow) 1988-07-13

Family

ID=14911325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55125488A Granted JPS5750152A (en) 1980-09-10 1980-09-10 Communication control processor

Country Status (1)

Country Link
JP (1) JPS5750152A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2555578B2 (ja) * 1987-01-16 1996-11-20 日本電気株式会社 通信制御装置

Also Published As

Publication number Publication date
JPS5750152A (en) 1982-03-24

Similar Documents

Publication Publication Date Title
US6581119B1 (en) Interrupt controller and a microcomputer incorporating this controller
JP3525518B2 (ja) データ転送装置
US4740910A (en) Multiprocessor system
JPS6335141B2 (enrdf_load_stackoverflow)
JPS58178468A (ja) デ−タ処理システムの割込方式
JP2001014266A (ja) Ｄｍａ転送回路およびｄｍａ転送方法
JPS5913769B2 (ja) チヤネル制御装置
JP2583169B2 (ja) 通信処理装置の運用プログラム切替方法
JPS6240565A (ja) メモリ制御方式
JPH09190317A (ja) 印刷装置および印刷方法
JPH05257903A (ja) マルチプロセッサシステム
JP3130892B2 (ja) 二重化システム
JP2871171B2 (ja) マイクロコンピュータ
JPH06139186A (ja) バス制御方式
JPH04127260A (ja) マルチプロセッサシステムの排他制御回路
JP2781999B2 (ja) マルチプロセツサシステムにおける共通データチヤネル装置起動方式
JP2836591B2 (ja) プロセッサ間バス伝送方法及びプロセッサ間バス伝送システム
JP2976343B2 (ja) 起動受け付け方法
JPH1115794A (ja) 並列データ処理装置
JPS6248871B2 (enrdf_load_stackoverflow)
JP2000067008A (ja) マルチプロセッサシステム
JPH0136126B2 (enrdf_load_stackoverflow)
JPH09297726A (ja) 割り込み排他処理方法
JPH02299048A (ja) 転送制御方式
JPH05100974A (ja) ソフトウエア・ダウンロード方式