JPS5750152A - Communication control processor - Google Patents
Communication control processorInfo
- Publication number
- JPS5750152A JPS5750152A JP55125488A JP12548880A JPS5750152A JP S5750152 A JPS5750152 A JP S5750152A JP 55125488 A JP55125488 A JP 55125488A JP 12548880 A JP12548880 A JP 12548880A JP S5750152 A JPS5750152 A JP S5750152A
- Authority
- JP
- Japan
- Prior art keywords
- adaptor
- control
- line
- flag
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Computer And Data Communications (AREA)
Abstract
PURPOSE:To achieve start control saving the hardware, by minimizing the effect on other line control adaptor. CONSTITUTION:A line common control section 1 consists of a control circuit 2, a start flag 3 storing the indication of start, an address register storing the line address indicated of starting, a scanning counter 5, a switching circuit 6 and a data buffer 7, and it is connected to a data bus 8 and a control bus 9. A line control adaptor 10 consists of an adaptor control circuit 11, a start-enable-flag 12 which displays the start reception enable being logic ''1'' when the preparation of reception of start information is finished, processing request flag 13 displaying the processing request, data buffer 14 in an adaptor, common bus 15 in the adaptor and a plurality of line interface circuits 16.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55125488A JPS5750152A (en) | 1980-09-10 | 1980-09-10 | Communication control processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55125488A JPS5750152A (en) | 1980-09-10 | 1980-09-10 | Communication control processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5750152A true JPS5750152A (en) | 1982-03-24 |
JPS6335141B2 JPS6335141B2 (en) | 1988-07-13 |
Family
ID=14911325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55125488A Granted JPS5750152A (en) | 1980-09-10 | 1980-09-10 | Communication control processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5750152A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63176048A (en) * | 1987-01-16 | 1988-07-20 | Nec Corp | Communication controller |
-
1980
- 1980-09-10 JP JP55125488A patent/JPS5750152A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63176048A (en) * | 1987-01-16 | 1988-07-20 | Nec Corp | Communication controller |
Also Published As
Publication number | Publication date |
---|---|
JPS6335141B2 (en) | 1988-07-13 |
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