JPS56169975A - Receiver for character broadcasting - Google Patents

Receiver for character broadcasting

Info

Publication number
JPS56169975A
JPS56169975A JP7277180A JP7277180A JPS56169975A JP S56169975 A JPS56169975 A JP S56169975A JP 7277180 A JP7277180 A JP 7277180A JP 7277180 A JP7277180 A JP 7277180A JP S56169975 A JPS56169975 A JP S56169975A
Authority
JP
Japan
Prior art keywords
memory
line period
during
information data
superimposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7277180A
Other languages
Japanese (ja)
Other versions
JPS6243592B2 (en
Inventor
Toyotaro Nishihara
Masutomi Oota
Kiyoshi Hiramatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7277180A priority Critical patent/JPS56169975A/en
Publication of JPS56169975A publication Critical patent/JPS56169975A/en
Publication of JPS6243592B2 publication Critical patent/JPS6243592B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards

Abstract

PURPOSE:To make unnecessary a buffer memory, by detaching a display memory from a CPU during the line period when information data is superimposed, and writing the information data on the space of storage area of a display memory. CONSTITUTION:A display memory 14 is connected to an address counter 7, at the line period when the address is superimposed on the information data with an address switching circuit 17, and connected to the output of an address switching circuit 13 during other line period. Further, the data input terminal of the memory 14 is connected to the output of a serial parallel conversion circuit 6 during the line period when the information data is superimposed and connected to a data bus 16 during other line period. With the constitution like this, the memory 14 is detached from a CPU substantially during the line period when the information data is superimposed and the information data is directly written in the storage area of space of the memory 14. Further, since the memory 14 is connected to the circuit 13 and the bus 16 during the next line period, the CPU10 reads out data from the memory 14 for display.
JP7277180A 1980-06-02 1980-06-02 Receiver for character broadcasting Granted JPS56169975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7277180A JPS56169975A (en) 1980-06-02 1980-06-02 Receiver for character broadcasting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7277180A JPS56169975A (en) 1980-06-02 1980-06-02 Receiver for character broadcasting

Publications (2)

Publication Number Publication Date
JPS56169975A true JPS56169975A (en) 1981-12-26
JPS6243592B2 JPS6243592B2 (en) 1987-09-16

Family

ID=13498965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7277180A Granted JPS56169975A (en) 1980-06-02 1980-06-02 Receiver for character broadcasting

Country Status (1)

Country Link
JP (1) JPS56169975A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5424532A (en) * 1977-07-27 1979-02-23 Hitachi Ltd Reception unit for still picture signal
JPS558138A (en) * 1978-07-03 1980-01-21 Fujitsu General Ltd Memory circuit of receiving unit
JPS5545246A (en) * 1978-09-25 1980-03-29 Matsushita Electric Ind Co Ltd Information receiving unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5424532A (en) * 1977-07-27 1979-02-23 Hitachi Ltd Reception unit for still picture signal
JPS558138A (en) * 1978-07-03 1980-01-21 Fujitsu General Ltd Memory circuit of receiving unit
JPS5545246A (en) * 1978-09-25 1980-03-29 Matsushita Electric Ind Co Ltd Information receiving unit

Also Published As

Publication number Publication date
JPS6243592B2 (en) 1987-09-16

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