JPS558138A - Memory circuit of receiving unit - Google Patents

Memory circuit of receiving unit

Info

Publication number
JPS558138A
JPS558138A JP8073078A JP8073078A JPS558138A JP S558138 A JPS558138 A JP S558138A JP 8073078 A JP8073078 A JP 8073078A JP 8073078 A JP8073078 A JP 8073078A JP S558138 A JPS558138 A JP S558138A
Authority
JP
Japan
Prior art keywords
memorize
circuit
memory
microcomputer
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8073078A
Other languages
Japanese (ja)
Inventor
Hiroshi Sobashima
Setsuo Okuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Gen Co Ltd
Original Assignee
Fujitsu General Ltd
Gen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gen Co Ltd filed Critical Fujitsu General Ltd
Priority to JP8073078A priority Critical patent/JPS558138A/en
Publication of JPS558138A publication Critical patent/JPS558138A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Systems (AREA)

Abstract

PURPOSE: To simplify the circuit constitution by using the microcomputer and thus memorizing temporarily the signals equivalent to one horizontal line into the buffer memory to be then memorized and accumulated slowly into the main memory until the next signal is supplied.
CONSTITUTION: The memory circuit for still picture signals including the microcomputer is inserted between video detection circuit 1 and video amplifier circuit 2 of the normal TV receiver. This memory circuit consists of the following component units: shift register 3 to memorize the 8 bits of the still picture and then send them to the next step; FC detection circuit 4 to detect framing code FC; latch 5 to draw in and memorize the data at the moment of the gate-on; buffer memory 6 to memorize the signals equivalent to one horizontal line in a high speed; address selection circuit 8 to perform the high-speed writing and low-speed reading for memory 6; large- capacity main memories 9(91∼96) to memorize the 8 bits memorized temporarily by one bit and thus to memorize one screen as a whole; address selection circuit 10; and shift register 12 respectively.
COPYRIGHT: (C)1980,JPO&Japio
JP8073078A 1978-07-03 1978-07-03 Memory circuit of receiving unit Pending JPS558138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8073078A JPS558138A (en) 1978-07-03 1978-07-03 Memory circuit of receiving unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8073078A JPS558138A (en) 1978-07-03 1978-07-03 Memory circuit of receiving unit

Publications (1)

Publication Number Publication Date
JPS558138A true JPS558138A (en) 1980-01-21

Family

ID=13726484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8073078A Pending JPS558138A (en) 1978-07-03 1978-07-03 Memory circuit of receiving unit

Country Status (1)

Country Link
JP (1) JPS558138A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56169975A (en) * 1980-06-02 1981-12-26 Hitachi Ltd Receiver for character broadcasting

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NATIONAL TECHNICAL REPORT=1975 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56169975A (en) * 1980-06-02 1981-12-26 Hitachi Ltd Receiver for character broadcasting
JPS6243592B2 (en) * 1980-06-02 1987-09-16 Hitachi Ltd

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