JPS5732196A - Channel converter - Google Patents

Channel converter

Info

Publication number
JPS5732196A
JPS5732196A JP10810180A JP10810180A JPS5732196A JP S5732196 A JPS5732196 A JP S5732196A JP 10810180 A JP10810180 A JP 10810180A JP 10810180 A JP10810180 A JP 10810180A JP S5732196 A JPS5732196 A JP S5732196A
Authority
JP
Japan
Prior art keywords
inputted
memories
output
memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10810180A
Other languages
Japanese (ja)
Other versions
JPS6237878B2 (en
Inventor
Yasuo Ito
Koji Yoshimoto
Yutaka Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10810180A priority Critical patent/JPS5732196A/en
Publication of JPS5732196A publication Critical patent/JPS5732196A/en
Publication of JPS6237878B2 publication Critical patent/JPS6237878B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Abstract

PURPOSE:To simplify circuit constitution by arranging a register at the output of a ROM and by feeding its output to the address of the ROM and also supplying it directly to the address of an audio signal memory, etc. CONSTITUTION:An audio signal modulated with an audio switch 12 is inputted to a memory 18 through an encoder 16. Signal information sampled with a signal switch 13 is inputted to a memory 19 through a delay circuit 17. On the other hand, the output of a ROM20' stored with a program realizing channel conversion is inputted to addresses of memories 18 and 19, and the ROM20' through a buffer register 36. Then, the latter half of the time slot of each channel is set as a writing time and the former half as a reading time; inputs are written in the memories 18 and 19 specified at random by an address sequence corresponding to the inputs, and read from the addresses of the specified memories 18 and 19 by another address sequence to convert the time slot.
JP10810180A 1980-08-06 1980-08-06 Channel converter Granted JPS5732196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10810180A JPS5732196A (en) 1980-08-06 1980-08-06 Channel converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10810180A JPS5732196A (en) 1980-08-06 1980-08-06 Channel converter

Publications (2)

Publication Number Publication Date
JPS5732196A true JPS5732196A (en) 1982-02-20
JPS6237878B2 JPS6237878B2 (en) 1987-08-14

Family

ID=14475891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10810180A Granted JPS5732196A (en) 1980-08-06 1980-08-06 Channel converter

Country Status (1)

Country Link
JP (1) JPS5732196A (en)

Also Published As

Publication number Publication date
JPS6237878B2 (en) 1987-08-14

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