JPS5650426A - Data transmission unit - Google Patents

Data transmission unit

Info

Publication number
JPS5650426A
JPS5650426A JP12634679A JP12634679A JPS5650426A JP S5650426 A JPS5650426 A JP S5650426A JP 12634679 A JP12634679 A JP 12634679A JP 12634679 A JP12634679 A JP 12634679A JP S5650426 A JPS5650426 A JP S5650426A
Authority
JP
Japan
Prior art keywords
interface
memory
arithmetic unit
data
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12634679A
Other languages
Japanese (ja)
Inventor
Ryuichi Sawafuji
Yukikoto Hosoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chino Works Ltd
Original Assignee
Chino Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chino Works Ltd filed Critical Chino Works Ltd
Priority to JP12634679A priority Critical patent/JPS5650426A/en
Publication of JPS5650426A publication Critical patent/JPS5650426A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To transmit a large quantity of data at a time, by providing a buffer memory in the peripheral device interface and by making it possible to use this buffer memory by the main arithmetic unit as well as the peripheral device interface.
CONSTITUTION: Main arithmetic unit 1 and peripheral device interface 2 are connected by control line 10, address bus 8, and data bus 9, and data is transmitted between arithmetic unit 1 and interface 2. This interface 2 is provided with private memory 42 and buffer memory 5, and switches 61 and 62 are switched to the device 32 side to make it possible to use memory 5 normally in interface 2 by central processing unit 32 of interface 2. In case that device 1 wants to occupy memory 5, the attention signal is transmitted to bus 8 from central process 31 of device 1 and is received by unit 32 of interface 2, and switches 61 and 62 are switched to transmit and receive the sense and request signals between device 32 and 31 through control line 10, thus making it possible to use memory 5.
COPYRIGHT: (C)1981,JPO&Japio
JP12634679A 1979-10-02 1979-10-02 Data transmission unit Pending JPS5650426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12634679A JPS5650426A (en) 1979-10-02 1979-10-02 Data transmission unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12634679A JPS5650426A (en) 1979-10-02 1979-10-02 Data transmission unit

Publications (1)

Publication Number Publication Date
JPS5650426A true JPS5650426A (en) 1981-05-07

Family

ID=14932883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12634679A Pending JPS5650426A (en) 1979-10-02 1979-10-02 Data transmission unit

Country Status (1)

Country Link
JP (1) JPS5650426A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124139A (en) * 1983-12-08 1985-07-03 Fujitsu Ltd Communication system of buffer memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124139A (en) * 1983-12-08 1985-07-03 Fujitsu Ltd Communication system of buffer memory
JPH0521376B2 (en) * 1983-12-08 1993-03-24 Fujitsu Ltd

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