JPS5622135A - Constitution control system - Google Patents

Constitution control system

Info

Publication number
JPS5622135A
JPS5622135A JP9796579A JP9796579A JPS5622135A JP S5622135 A JPS5622135 A JP S5622135A JP 9796579 A JP9796579 A JP 9796579A JP 9796579 A JP9796579 A JP 9796579A JP S5622135 A JPS5622135 A JP S5622135A
Authority
JP
Japan
Prior art keywords
cfr
svp2
register
bits
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9796579A
Other languages
Japanese (ja)
Other versions
JPS6239455B2 (en
Inventor
Masao Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9796579A priority Critical patent/JPS5622135A/en
Publication of JPS5622135A publication Critical patent/JPS5622135A/en
Publication of JPS6239455B2 publication Critical patent/JPS6239455B2/ja
Granted legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To make it unnecessary for the service processor to be conscious of the physical conditions of each unit forming the system and at the same time simplify the software, by providing the constitution control register.
CONSTITUTION: Constitution control register 19 is provided to central processor CPU04-0. When service processor SVP2 delivers "10" as bits CFR0 and CER1 each, input G1 of memory control unit MCU1 is "0". And "10" is written into bits CFR0 and CFR1 of register 19. In case the contents of register 19 are read out, the contents are read directly into SVP2. Then in case SVP2 and MCU2 of other systems, i.e., input G1 is defined as "1", "01" is written into bits CFR0 and CFR1 of register 19 when SVP2 delivers "10" as bits CFR0 and CFR1. And in case register 19 is read, "10" and "01" are reversed to be read into SVP2 each. Accordingly, SVP2 does not need two kinds of data "10" and "01".
COPYRIGHT: (C)1981,JPO&Japio
JP9796579A 1979-07-31 1979-07-31 Constitution control system Granted JPS5622135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9796579A JPS5622135A (en) 1979-07-31 1979-07-31 Constitution control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9796579A JPS5622135A (en) 1979-07-31 1979-07-31 Constitution control system

Publications (2)

Publication Number Publication Date
JPS5622135A true JPS5622135A (en) 1981-03-02
JPS6239455B2 JPS6239455B2 (en) 1987-08-24

Family

ID=14206374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9796579A Granted JPS5622135A (en) 1979-07-31 1979-07-31 Constitution control system

Country Status (1)

Country Link
JP (1) JPS5622135A (en)

Also Published As

Publication number Publication date
JPS6239455B2 (en) 1987-08-24

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