JPS5547548A - Memory employing and managing system - Google Patents

Memory employing and managing system

Info

Publication number
JPS5547548A
JPS5547548A JP12655079A JP12655079A JPS5547548A JP S5547548 A JPS5547548 A JP S5547548A JP 12655079 A JP12655079 A JP 12655079A JP 12655079 A JP12655079 A JP 12655079A JP S5547548 A JPS5547548 A JP S5547548A
Authority
JP
Japan
Prior art keywords
memory
bits
attribute
accommodated
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12655079A
Other languages
Japanese (ja)
Other versions
JPS5833968B2 (en
Inventor
Akira Maeda
Misao Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54126550A priority Critical patent/JPS5833968B2/en
Publication of JPS5547548A publication Critical patent/JPS5547548A/en
Publication of JPS5833968B2 publication Critical patent/JPS5833968B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To select the discharged information easily by providing two shift registers corresponding to the respective bit in the respective entry in the table in the processor in which a part of the information showing the attribute of the data in the memory is accommodated.
CONSTITUTION: The information showing the attribute of the respective data in the memory 6 in the table 50 in the memory controller 5 is accommodated. When the data 61 in the memory 6 is made access by the processors 1W4, the first register's bit corresponding to the entry of the tables 10W40 in the processors 1W4 in which the information showing the attribute is accommodated is set at "1". When the bits more than a predetermined number become "1", all the bits are transmitted to the second register and all the bits are made to be 0. Then, one content of the entry corresponding to the bit in which both the bits corresponding to the first and the second registers become "0" is adapted to be discharged.
COPYRIGHT: (C)1980,JPO&Japio
JP54126550A 1979-10-01 1979-10-01 Memory usage management method Expired JPS5833968B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54126550A JPS5833968B2 (en) 1979-10-01 1979-10-01 Memory usage management method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54126550A JPS5833968B2 (en) 1979-10-01 1979-10-01 Memory usage management method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP50065539A Division JPS51141544A (en) 1975-05-31 1975-05-31 Method of memory utilization control

Publications (2)

Publication Number Publication Date
JPS5547548A true JPS5547548A (en) 1980-04-04
JPS5833968B2 JPS5833968B2 (en) 1983-07-23

Family

ID=14937942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54126550A Expired JPS5833968B2 (en) 1979-10-01 1979-10-01 Memory usage management method

Country Status (1)

Country Link
JP (1) JPS5833968B2 (en)

Also Published As

Publication number Publication date
JPS5833968B2 (en) 1983-07-23

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