JPS5833968B2 - Memory usage management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory usage management system, and more particularly to a management system for a table in a processor that stores information indicating attributes of data in memory.

In general, when multiple processors share the same data in shared memory and use the shared memory by expanding it virtually, when this shared data is flushed out of the shared memory, each processor It is necessary to rewrite the table that stores information indicating what kind of data is stored in the shared memory, that is, the attributes of the data.

The simplest method is to invalidate the contents of the table in each processor when even one piece of shared data is removed, and then rewrite the contents.

Although this method is simple, it involves a lot of unnecessary operations.

Also, these tables usually do not have a large capacity;
It is not possible to store information about the attributes of all data in memory.

Therefore, it is common practice to store all data attribute information in a table in the memory controller, and to import only relatively frequently used data into a table in the processor.

At this time, which data attribute information should be imported?
In other words, deciding what information to push off the table is not easy.

Conventionally, methods include randomly deciding which information to export, or selecting information that has not been used in any recent amount.

The former uses simple hardware to implement it, but ignores the locality of the program.

The latter makes effective use of program locality, but conventional methods of this type tend to complicate the hardware.

The present invention has been made in consideration of the above points, and its purpose is to create a table in a processor that stores attributes of data in memory using relatively simple hardware that is likely to be used in the relatively near future. To provide a memory use management method that efficiently manages information and other information that is not desired to be deleted.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a multiprocessor system for explaining the outline of an embodiment of the present invention, in which 1 to 4 represent processors, 5 represents a memory controller, and 6 represents a shared memory.

When data in the memory 6 is shared in such a multiprocessor system, information indicating what kind of data is stored in the memory 6, that is, attributes stored in tables in the processors 1 to 4, is used. There must always be a correspondence between the information shown and the data in the memory 6.

Now, suppose that processors 1 and 2 share the same data 61 in memory 6 as shown in FIG.

Information regarding the attributes of this data (where in the memory the data 61 is located, what properties it has, etc.)
.

In this state, for some reason one of the processors, for example 1
If the user changes the attributes of the data 61, the contents of the table 20 in the processor 2 will become false.

In this state, correct operation of the system cannot be expected, and the contents of the table 20 must be corrected.

In order to achieve this, each processor 1~
4 are provided with 1-bit registers 101-104 and registers 201-204 for storing data names.

A processor that attempts to change the attributes of shared data here,
In FIG. 2, the processor 1 that wishes to change the attributes of data 61 sends the name of the data 61 whose attributes are to be changed to the memory controller 5.

After confirming that all 1-bit registers 101 to 104 in each processor 1 to 4 are in the "■" state, the memory controller 5 transfers the data name sent from processor 1 to all processors 1 to 4. register 20 of
1 to 204, 1-bit registers 101 to 10
4 are all set to 0'' state.

In this way, 1-bit registers 101 to 104 are set to “O”.
When set to the state, each processor 1-4 erases the designated data name from its own table 10-40.

After erasing, 1-bit registers 101 to 104 are set to “1”.
``state.

When the memory controller 5 detects that all of the registers 101 to 104 are in the 1'' state, it notifies the processor 1 that has attempted to change the attribute, and only then does that processor 1 change the attribute of the shared data 61. be able to.

The new attributes after the change are stored in a table 50 within the memory table 5.

If the processors 1 to 4 wish to know the new attributes of the data 61 later, they can refer to this table 60.

By doing so, it is possible to establish a correspondence between the data in the shared memory 6 and the information indicating the attributes of the data taken into the tables 10 to 40 in the processors 1 to 4.

Now, the tables 10 to 40 that store information regarding the attributes of data in each of the processors 1 to 4 shown in FIG. 2 may not have a sufficiently large capacity and may not be able to store the attributes of all data in the memory 5 .

In this case, the table 50 in the memory controller 5
A part of the information indicating the attributes of all the data in the memory 6 stored in the processors 1 to 4 is stored in the tables 10 to
It will be transferred to 40.

At this time, it is a good idea to store information regarding attributes of data that will be frequently used in the future in the tables 10-40.

As a property of programs in computers, there is a tendency to refer to data in a relatively limited range, that is, a tendency for programs to be localized.
It is possible to increase the probability that information is present in tables 10 to 40 with small capacities within .about.4.

In other words, only information related to attributes of data that has been accessed recently is stored in tables 10 to 40, or in other words, information that has been least recently used is stored in tables 10 to 40.
All you have to do is try to push it out from 40.

Therefore, in the present invention, first, second, and third registers 301, 302, and 303 are installed as shown in FIG.

Each bit of these registers 301, 302 and 303 corresponds to tables 10 to 4 in processors 1 to 4 in FIG.
40 entries 11゜12.13 to 41, 42.43
It corresponds to

When processors 1-4 access data in memory 6, they refer to the contents of tables 10-40 within themselves in order to know the attributes of that data.

At this time, the bit in the register 301 corresponding to the referenced entry in tables 10 to 40 is set to "1".

If more than a certain number of bits in register 301 (
For example, if the majority) becomes “■”, the detection circuit 30 detects this.
4 is detected, the OR circuit 305 calculates the logical sum of the contents of the register 301 and the contents of the register 303, transfers this logical sum to the register 302, and the register 301 itself clears all bits to the "0" state. a.

Note that, in the register 303, among the entries in the tables 10 to 40, only the bit corresponding to a specific entry storing information that is not to be deleted is set to 1''.

Here, if tables 10-40 in processors 1-4
If you are faced with the need to extract any one piece of information from
The OR circuit 306 calculates the logical sum of the corresponding bits of the contents of the registers 301 and 302, and selects one of the entries in tables 10 to 40 corresponding to the bit whose logical sum is 10''. All you have to do is track down the content.

By doing this, it is possible to leave information that has been referenced relatively recently in the tables 10 to 40 in the processors 1 to 4, and even if it has not been referenced recently, the information in the register 303 " It is possible to prevent specific data in tables 10 to 40 corresponding to the bits set with "2" from being evicted.

As explained in detail above, according to the present invention, the comparison is mainly based on three shift registers in which each bit corresponds to each entry of a table in the processor that stores part of the information indicating the attributes of data in the memory. By providing simple hardware, when it becomes necessary to remove part of the contents of the table in the processor and rewrite it with new information, it is possible to remove part of the contents of the table in the processor, and to rewrite it with new information. Moreover, it has the advantage of being able to easily select information that will not cause any problems even if it is deleted.

[Brief explanation of drawings]

Figure 1 is a schematic configuration diagram of a multiprocessor system that shares memory, Figure 2 is a diagram showing how data is shared in a multiprocessor system, and Figure 3 shows information captured in memory and processors in a multiprocessor system. FIG. 4, which is a diagram showing a matching method, is a circuit diagram of a circuit that selects information that is relatively unused from among information stored in a table in a processor, which is a main part of an embodiment of the present invention. . 1 to 4...Flosser, 5...Memory controller, 6...Memory, 10 to 40...
...Table, 50...Table, 301
, 302, 303... register, 304...
...Detection circuit, 305, 306...OR circuit.

Claims (1)

[Claims] 1. A memory controller having a table storing information indicating the attributes of each data in the memory, and a table storing part of the contents of the table in the memory controller in a processor that uses the data in the memory. , has first, second, and third registers each corresponding to each entry in this table, and data in the memory in which information indicating an attribute is stored in the table in the processor is stored in the table in the processor. When accessed,
The bit of the first register corresponding to the entry of the table in the processor that stores the information indicating the attribute is set to "1". When a certain number or more of the bits of the first register become "1", The logical sum of the contents of the first register and the contents of the third register whose bit corresponding to a specific entry of the table in the processor is set to '1'' is transferred to the second register; If it becomes necessary to clear all bits of a register to the "0" state and flush out part of the contents stored in the table in the processor, the corresponding bits of the first and second registers are both set to "0". A memory usage management method characterized in that the contents of one of the entries corresponding to the bit in the "state" are deleted.