JPS63199341U - - Google Patents

Info

Publication number
JPS63199341U
JPS63199341U JP1988056781U JP5678188U JPS63199341U JP S63199341 U JPS63199341 U JP S63199341U JP 1988056781 U JP1988056781 U JP 1988056781U JP 5678188 U JP5678188 U JP 5678188U JP S63199341 U JPS63199341 U JP S63199341U
Authority
JP
Japan
Prior art keywords
instruction
prefetch
request
tag
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988056781U
Other languages
English (en)
Other versions
JP2504830Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS63199341U publication Critical patent/JPS63199341U/ja
Application granted granted Critical
Publication of JP2504830Y2 publication Critical patent/JP2504830Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Description

【図面の簡単な説明】
第１図は、本考案に従つたパイプライン式処理
装置のブロツク図、第２図は、本考案に従つたブ
ランチ操作を示す流れ図、第３図は、本考案に従
つた命令実行を示す流れ図、第４図は、本考案の
プリフエツチ操作を示す流れ図、第５図は、本考
案の戻りタグ操作を示す流れ図、第６図は、通常
のブランチ操作の命令フエツチ、解読および実行
を示すタイミング図、第７図は、本考案に従つた
命令実行のより詳しいタイミング図、第８図は、
ブランチ・実行の開始時における命令プリフエツ
チ・バツフアの可能な８つの状態を示す図、第９
図は、本考案に従つた命令プリフエツチ・バツフ
アの操作を示すブロツク図である。 １０…パイプライン式処理装置、１１…命令プ
リフエツチ・バツフア（ＩＰＢ）、１２…記憶チ
ヤネル、１３…記憶制御装置、１４…記憶装置、
１５〜１８…命令プリフエツチ・レジスタ、１９
…ブランチ・タグ・レジスタ（ＢＴＲ）、２１…
制御論理、３７…実行ユニツト。

Claims (1)

  1. 【実用新案登録請求の範囲】 複数の命令プリフエツチ・レジスタから成る命
    令プリフエツチ・バツフアを備え、少くとも１つ
    のブランチ命令を含む複数の命令を、記憶装置か
    ら前記命令プリフエツチ・バツフアへプリフエツ
    チするように構成されているデータ処理装置にお
    いて、 ブランチ命令を実行する度にその現在の値が変
    更されるような制御タグを発生する制御タグ発生
    手段と、 前記複数の命令プリフエツチ・バツフアのどれ
    を各命令のプリフエツチ要求のために使用すべき
    かを選択し且つ該選択された命令プリフエツチ・
    レジスタの識別タグを該各命令ごとに発生する識
    別タグ発生手段と、 各命令のプリフエツチ要求に前記制御タグ及び
    前記識別タグを付加してこれを前記記憶装置へ送
    信する要求送信手段と、 各命令のプリフエツチ要求が前記記憶装置へ送
    信される際、該各命令のプリフエツチ要求のため
    に選択された前記命令プリフエツチ・レジスタに
    未処理フエツチ・ビツトをセツトする論理手段と
    、 前記記憶装置からプリフエツチされた各命令に
    付随する前記制御タグの値と前記制御タグ発生手
    段における前記制御タグの現在の値を比較し、こ
    れらの値が等しい場合は、該各命令をこれに付随
    する前記識別タグによつて識別された前記命令プ
    リフエツチ・レジスタに格納し、さもなければ該
    命令プリフエツチ・レジスタにセツトされている
    前記未処理フエツチ・ビツトをリセツトする制御
    手段とを備えて成るデータ処理装置。
JP1988056781U 1984-10-31 1988-04-28 デ―タ処理装置 Expired - Lifetime JP2504830Y2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/666,790 US4775927A (en) 1984-10-31 1984-10-31 Processor including fetch operation for branch instruction with control tag
US666790 1984-10-31

Publications (2)

Publication Number Publication Date
JPS63199341U true JPS63199341U (ja) 1988-12-22
JP2504830Y2 JP2504830Y2 (ja) 1996-07-24

Family

ID=24675490

Family Applications (2)

Application Number Title Priority Date Filing Date
JP60179565A Pending JPS61109147A (ja) 1984-10-31 1985-08-16 命令フェッチ及び実行制御方法
JP1988056781U Expired - Lifetime JP2504830Y2 (ja) 1984-10-31 1988-04-28 デ―タ処理装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP60179565A Pending JPS61109147A (ja) 1984-10-31 1985-08-16 命令フェッチ及び実行制御方法

Country Status (5)

Country Link
US (1) US4775927A (ja)
EP (2) EP0448499B1 (ja)
JP (2) JPS61109147A (ja)
CA (1) CA1227877A (ja)
DE (2) DE3586235T2 (ja)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239081B1 (en) * 1986-03-26 1995-09-06 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel
JPH0731615B2 (ja) * 1986-04-18 1995-04-10 日本電気株式会社 情報処理装置
JPS6393038A (ja) * 1986-10-07 1988-04-23 Mitsubishi Electric Corp 計算機
US5117489A (en) * 1987-04-22 1992-05-26 Mitsubishi Denki Kabushiki Kaisha Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet
US4942520A (en) * 1987-07-31 1990-07-17 Prime Computer, Inc. Method and apparatus for indexing, accessing and updating a memory
JPS6488844A (en) * 1987-09-30 1989-04-03 Takeshi Sakamura Data processor
JPH0769812B2 (ja) * 1987-12-29 1995-07-31 富士通株式会社 データ処理装置
US5155818A (en) * 1988-09-28 1992-10-13 Data General Corporation Unconditional wide branch instruction acceleration
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5768575A (en) * 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
US5781753A (en) 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
JPH03139726A (ja) * 1989-10-26 1991-06-13 Hitachi Ltd 命令読出し制御方式
US5028186A (en) * 1990-01-29 1991-07-02 Mechanical Plastics Corp. Hollow wall anchor with enhanced holding strength
US5255371A (en) * 1990-04-02 1993-10-19 Unisys Corporation Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands
JP2544027B2 (ja) * 1990-05-24 1996-10-16 株式会社東芝 低消費電力型プログラマブルロジックアレイおよびそれを用いた情報処理装置
CA2045735A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Computer performance by eliminating branches
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
JP2761688B2 (ja) * 1992-02-07 1998-06-04 三菱電機株式会社 データ処理装置
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
JP3637920B2 (ja) 1992-05-01 2005-04-13 セイコーエプソン株式会社 スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JP2596712B2 (ja) * 1993-07-01 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 近接した分岐命令を含む命令の実行を管理するシステム及び方法
US6065108A (en) * 1996-01-24 2000-05-16 Sun Microsystems Inc Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same
US5796998A (en) * 1996-11-21 1998-08-18 International Business Machines Corporation Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system
EP0855645A3 (en) * 1996-12-31 2000-05-24 Texas Instruments Incorporated System and method for speculative execution of instructions with data prefetch
US6157998A (en) 1998-04-03 2000-12-05 Motorola Inc. Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers
EP1050811A1 (en) * 1999-05-03 2000-11-08 STMicroelectronics SA Branching in a computer system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120735A (en) * 1976-04-05 1977-10-11 Agency Of Ind Science & Technol Microporogram control unit
JPS5582357A (en) * 1978-12-15 1980-06-21 Nec Corp Information processing unit
JPS581247A (ja) * 1981-06-26 1983-01-06 Mitsubishi Electric Corp 命令先取り制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5021821B1 (ja) * 1968-10-31 1975-07-25
US4155120A (en) * 1977-12-01 1979-05-15 Burroughs Corporation Apparatus and method for controlling microinstruction sequencing by selectively inhibiting microinstruction execution
AU529675B2 (en) * 1977-12-07 1983-06-16 Honeywell Information Systems Incorp. Cache memory unit
US4179737A (en) * 1977-12-23 1979-12-18 Burroughs Corporation Means and methods for providing greater speed and flexibility of microinstruction sequencing
US4360868A (en) * 1978-12-06 1982-11-23 Data General Corporation Instruction prefetch means having first and second register for storing and providing a current PC while generating a next PC
JPS56129950A (en) * 1980-03-07 1981-10-12 Hitachi Ltd Information processor
US4348724A (en) * 1980-04-15 1982-09-07 Honeywell Information Systems Inc. Address pairing apparatus for a control store of a data processing system
JPS56149646A (en) * 1980-04-21 1981-11-19 Toshiba Corp Operation controller
US4430706A (en) * 1980-10-27 1984-02-07 Burroughs Corporation Branch prediction apparatus and method for a data processing system
JPS57193843A (en) * 1981-05-22 1982-11-29 Mitsubishi Electric Corp Pipeline computer
US4435756A (en) * 1981-12-03 1984-03-06 Burroughs Corporation Branch predicting computer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120735A (en) * 1976-04-05 1977-10-11 Agency Of Ind Science & Technol Microporogram control unit
JPS5582357A (en) * 1978-12-15 1980-06-21 Nec Corp Information processing unit
JPS581247A (ja) * 1981-06-26 1983-01-06 Mitsubishi Electric Corp 命令先取り制御方法

Also Published As

Publication number Publication date
EP0180725A3 (en) 1988-10-05
EP0448499A3 (en) 1992-05-06
EP0448499B1 (en) 1998-04-08
JP2504830Y2 (ja) 1996-07-24
DE3586235D1 (de) 1992-07-23
JPS61109147A (ja) 1986-05-27
DE3586235T2 (de) 1993-02-11
DE3588182T2 (de) 1998-10-29
EP0180725B1 (en) 1992-06-17
DE3588182D1 (de) 1998-05-14
US4775927A (en) 1988-10-04
CA1227877A (en) 1987-10-06
EP0180725A2 (en) 1986-05-14
EP0448499A2 (en) 1991-09-25

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