JPS63181396A - Method of mounting semiconductor - Google Patents
Method of mounting semiconductorInfo
- Publication number
- JPS63181396A JPS63181396A JP1247287A JP1247287A JPS63181396A JP S63181396 A JPS63181396 A JP S63181396A JP 1247287 A JP1247287 A JP 1247287A JP 1247287 A JP1247287 A JP 1247287A JP S63181396 A JPS63181396 A JP S63181396A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- semiconductor
- lead
- board
- insulating ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000000034 method Methods 0.000 title claims description 8
- 239000008188 pellet Substances 0.000 claims description 26
- 239000000919 ceramic Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000003110 anti-inflammatory effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000000935 solvent evaporation Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、半導体の実装方法に関し、特に半導体分野で
利用さルるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor mounting method, and is particularly applicable to the semiconductor field.
C#来の技術1
1Q IS工等の半導体が塔載される回路プリント基板
において、その基板の上面に露呈し配置されている接続
端子に、回路素子を有した半導体のペレットから延び出
した各リードの先端部を溶接して接続する場会、従来は
半導体のペレットを基板上の搭載部に位置させ、上記ペ
レットの各リードの先端部を上記基板上の接続端子に重
ねて、溶接によって接続する工うにしてい7ta
上記ペレツトは、打ち抜き形改時に、各リードが2段に
折り曲げられ折曲段部が形成さrt、、基板上の接続端
子と密着出来るようになっている0しかし、上記ペレッ
トの各リードの厚みは、30〜35μm程度と薄い九め
、特に上記折曲段部が形成や折れ等が生じ烏<、その九
め2液混曾型のエポキシ系接着剤や紫外線硬化型、ま友
は溶剤蒸発型の接着剤等を補強用接着剤として少なくと
も上記リードの折曲段部に塗布し、その硬化によって上
記変位や折れ等を防止するようにしてい7jaところが
上記2液混廿型のエポキシ系の補強用接着剤、は、硬化
前には低粘度であるtめ、上記す−ドの必要部分以上に
塗布しても流れ出して基板上の必要部分以上に広がって
必要補強量を困難であるばかやではなく1手間と時間が
かかる。また。C# Latest technology 1 1Q In a circuit printed board on which a semiconductor such as an IS engineer is mounted, each connecting terminal exposed and placed on the top surface of the board is connected to each extending from a semiconductor pellet having a circuit element. When connecting the tips of the leads by welding, conventionally a semiconductor pellet is placed on the mounting part on the board, the tips of each lead of the pellet are overlapped with the connection terminals on the board, and the connection is made by welding. When changing the shape of the punched pellet, each lead is bent into two steps to form a folded stepped portion, so that it can be brought into close contact with the connecting terminal on the board. The thickness of each lead of the pellet is thin, about 30 to 35 μm, and the above-mentioned folded step part may be formed or broken. , Mayu applies a solvent evaporation adhesive or the like as a reinforcing adhesive to at least the bent step part of the lead, and prevents the displacement or bending by curing it. The epoxy reinforcing adhesive for the mold has a low viscosity before it hardens, so even if you apply it to more than the required area of the board, it will flow and spread beyond the required area on the board, reducing the required amount of reinforcement. It's not stupid or difficult, but it takes effort and time. Also.
半導体素子の高集積化、及び高速化が飛躍的に進み、素
子の発熱量が増大することにより1機能の低下などが生
じ、動作の長期間にわ几る保証がむずかしくなってきて
いる。その几め、フィンや各リードからの熱放散などが
考えられているが、熱膨張係数の差にょう熱応力発生や
補強用接着剤が熱放散を妨げるなどの問題があっ7t。BACKGROUND ART As the integration and speed of semiconductor devices have dramatically increased, the amount of heat generated by the devices has increased, resulting in a decline in one function, making it difficult to guarantee long-term operation. As a solution, heat dissipation from the fins and each lead has been considered, but there are problems such as thermal stress generation due to differences in thermal expansion coefficients and reinforcing adhesives that impede heat dissipation.
〔発明が解決しようとする問題点)
本発明の目的は、上記の点において少なくとも上記半導
体の各リードの折曲段部を覆う絶縁性セラミックを用い
ることによって、上記欠点を解消し九半導体の実装方法
を提供することにある。[Problems to be Solved by the Invention] An object of the present invention is to solve the above-mentioned drawbacks by using an insulating ceramic that covers at least the bending steps of each lead of the semiconductor, and to improve the packaging of the semiconductor. The purpose is to provide a method.
(問題点を解決するための手段および作用)本発明は、
上記目的を達成するために、上記半導体ペレットの上面
を露呈させる開孔有し、少なくとも同ペレットの各リー
ドの折曲段部を覆う大きさの絶縁性セラミックを回路基
板に半田を介して溶着し、上記半導体のリードの補強を
行ない熱放散性を向上きせること全特徴とする。(Means and effects for solving the problems) The present invention has the following features:
In order to achieve the above object, an insulating ceramic having an opening exposing the upper surface of the semiconductor pellet and having a size that at least covers the bent step of each lead of the pellet is welded to the circuit board via solder. The main feature is that the leads of the semiconductor described above are reinforced to improve heat dissipation.
(実施例) 以下本発明を図示の実施例に基づいて説明する。(Example) The present invention will be explained below based on illustrated embodiments.
第1図は本発明の一実施例を示す半導体装方法?説明す
る斜視図である0図において符号11は回路プリント基
板であわ、この基板11には内部に配線され友プリント
回路の接続端子12及び絶縁性セラミック13ヲ基板1
1と固定するための基板側パット14が配置されている
0符号15は工q等の半導体であり1回路素子を形成し
之工Oペレット16とこのペレット16に基端部全接続
さ11、会成樹脂等により封止された後、同ペレット1
6から延び出しt多数のリード17で構成さnて^る。FIG. 1 shows a semiconductor packaging method showing an embodiment of the present invention. In Figure 0, which is a perspective view for explanation, reference numeral 11 denotes a circuit printed board, and this board 11 has wiring inside it, connection terminals 12 of a companion printed circuit, and an insulating ceramic 13.
The reference numeral 15 on which the pad 14 on the substrate side for fixing with the substrate 1 is arranged is a semiconductor such as 1, which forms one circuit element, and the entire proximal end is connected to the pellet 16 and this pellet 16. After being sealed with synthetic resin etc., the pellet 1
It consists of a large number of leads 17 extending from the lead 6.
上記り一ド17は中程で2段に折り曲げられて折曲段部
17aが形成さnており、その先端の下段部が上記基板
11上の各接続端子12に相対して重甘し、溶接さfi
るようになりている。The board 17 is bent in two steps in the middle to form a bent step portion 17a, and the lower end portion of the bent step portion 17a is heavy in opposition to each connection terminal 12 on the board 11. welded fi
It's starting to look like this.
絶癲性セラミック13には、少なくとも上記工Cペレッ
ト16の各リード17の折曲段部17a を覆う開孔1
8を有し、その厚みは基板11からペレット16の上面
と同程度の厚さか望ましい。The anti-inflammatory ceramic 13 has an opening 1 that covers at least the bent step portion 17a of each lead 17 of the engineered C pellet 16.
8, and its thickness is preferably about the same thickness as the top surface of the pellet 16 from the substrate 11.
次に、以上のように構成された本発明の半導体の実装方
法を説明する。すなわち第2図に示すように回路プリン
ト基板21の各接続端子22上に対応する半導体25の
リード27の先端部を重甘し。Next, a semiconductor mounting method of the present invention configured as above will be explained. That is, as shown in FIG. 2, the tips of the leads 27 of the semiconductor 25 corresponding to each connection terminal 22 of the circuit printed board 21 are tightly attached.
次いで半導体25のIOペレット26の上面部分が上記
絶縁性セラミック23の開孔28内にはめ込まn9.基
板側パッド24と固定バット29ヲ重合させる0この状
態で加熱炉内を通過させる0すると、第3図に示すよう
に固定パッド39が溶融し、基板側パット34が溶着し
、上記リード37の折曲段部27aとその近傍は強固に
補強され、上記リード37と絶縁性セラミック33の接
殖により熱放散性か向上する@従って、上記し几従来の
この種の半導体の欠点は解消される・
第4図は、上記第1.2図における絶縁性セラミック4
3を厚くシ、開孔48を有しない場什であって、ペレッ
面46F而2絶縁性セラミック43との接触により、さ
らに熱欲散を向上するものである0薦5図は、第4図に
おける絶縁性セラミツク43上面に金属フィン50を取
っ付けることによねペレット56の冷却効果を高めるも
のであって、なおかつペレット56上面に直接、接着し
t場合よ、りも熱応力が大幅に低減する。また、第6図
のように絶縁性セラミック63に開孔68ヲ有している
もので、ペレット66上面と金属フィン6oが直接接触
するようにしてもよい◎このflJI会、ペレット66
上面と金属フィン60の間゛には、接着剤を使用しなく
ともよいことになる。Next, the upper surface portion of the IO pellet 26 of the semiconductor 25 is fitted into the opening 28 of the insulating ceramic 23 n9. When the substrate-side pad 24 and the fixed bat 29 are polymerized and passed through a heating furnace in this state, the fixed pad 39 is melted and the substrate-side pad 34 is welded, as shown in FIG. The bent step portion 27a and its vicinity are strongly reinforced, and heat dissipation is improved by the contact between the lead 37 and the insulating ceramic 33. Therefore, the drawbacks of the conventional semiconductor of this type described above are eliminated. - Figure 4 shows the insulating ceramic 4 in Figure 1.2 above.
Recommendation 5, in which the pellet surface 46F is thick and does not have the hole 48, further improves heat dissipation by contacting the pellet surface 46F with the insulating ceramic 43 is shown in FIG. By attaching the metal fins 50 to the top surface of the insulating ceramic 43, the cooling effect of the pellets 56 is enhanced, and thermal stress is significantly reduced compared to when the metal fins 50 are directly bonded to the top surface of the pellets 56. . Alternatively, as shown in FIG. 6, the insulating ceramic 63 may have an opening 68 so that the upper surface of the pellet 66 and the metal fin 6o are in direct contact.
There is no need to use adhesive between the upper surface and the metal fins 60.
なお、上記絶縁性セラミックは工Cペレットの形状に応
じて、任意の円形、多角形にした方が望ましい。Note that it is preferable that the insulating ceramic has any circular or polygonal shape depending on the shape of the engineered C pellets.
以上説明し友ように1本発明によれば構造の簡単な絶縁
性セラミックを用いるだけで、工0リードフレームの補
強を簡単に出来るだけでなく、同時に放熱性にも優れ、
極めて信頼性の高い安定したものを供給する。As explained above, according to the present invention, by simply using an insulating ceramic with a simple structure, it is not only possible to easily reinforce the lead frame, but also it has excellent heat dissipation.
We supply extremely reliable and stable products.
第1図は本発明の一実施例を示す半導体の実装方法の分
解斜視図、第2図および第3図は、上記第1図における
半導体の実装工程t−y7zす拡大断面図、第4図、第
5図および8g6図は本発明に用いらnる他の高放熱構
造を示す断面図である。
11、12.31.41.51.61・・・ 回路プリ
ント基板(基板) 、 12.22.32.42.52
.62・・・接続端子、13、23.33.43.53
.63・・・絶縁性セラミック。
14、24.34.44.54.64・・・基板側パッ
ド、15゜25、35.45.55.65・・・半導体
、 16.26.36.46゜56、66・・・ICペ
レット(ペレットl 、 17.27゜37.47,
57.67・・・リード、 18.28.38・・・
開孔。
29、39.49.59.69・・・固定パッド、
50.60・・・金属フィン◎
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
第 1 図FIG. 1 is an exploded perspective view of a semiconductor mounting method showing an embodiment of the present invention, FIGS. 2 and 3 are enlarged cross-sectional views of the semiconductor mounting process t-y7z in FIG. 1, and FIG. , FIG. 5 and FIG. 8g6 are cross-sectional views showing other high heat dissipation structures used in the present invention. 11, 12.31.41.51.61... Circuit printed board (board), 12.22.32.42.52
.. 62...Connection terminal, 13, 23.33.43.53
.. 63...Insulating ceramic. 14, 24.34.44.54.64...Substrate side pad, 15°25, 35.45.55.65...Semiconductor, 16.26.36.46°56,66...IC pellet (Pellet l, 17.27°37.47,
57.67...Reed, 18.28.38...
Open hole. 29, 39.49.59.69... fixed pad,
50.60...Metal fin◎ Agent Patent attorney Noriyuki Chika Yudo Kikuo Takehana Figure 1
Claims (1)
び出していて折曲段部を有し、先端部を基板上に露呈し
た各接続端子に溶接する各リードとからなる半導体と、
上記ペレットの上面を露出させる開孔と少なくとも上記
各リードの折曲段部を覆う容量を有していて、上記ペレ
ットの周囲の上記リード上に載置される絶縁性セラミッ
クとからなり、前記各リードの折曲段部を覆って、前記
半導体を前記結線性セラミックで固定することを特徴と
する半導体の実装方法。A semiconductor consisting of a pellet having a circuit element formed thereon, and each lead extending from the pellet and having a bent step, the tip end of which is welded to each connection terminal exposed on a substrate;
The pellet has an aperture that exposes the upper surface of the pellet, and an insulating ceramic that has a capacity to cover at least the bent step of each of the leads and is placed on the lead around the pellet. A method for mounting a semiconductor, comprising: fixing the semiconductor with the wire-connectable ceramic, covering the bent step portion of the lead.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1247287A JPS63181396A (en) | 1987-01-23 | 1987-01-23 | Method of mounting semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1247287A JPS63181396A (en) | 1987-01-23 | 1987-01-23 | Method of mounting semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63181396A true JPS63181396A (en) | 1988-07-26 |
Family
ID=11806313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1247287A Pending JPS63181396A (en) | 1987-01-23 | 1987-01-23 | Method of mounting semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63181396A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0195778U (en) * | 1987-12-18 | 1989-06-26 | ||
JP2010283085A (en) * | 2009-06-03 | 2010-12-16 | Toshiba Corp | Electronic apparatus |
WO2023162029A1 (en) * | 2022-02-22 | 2023-08-31 | 三菱電機株式会社 | Drive device and air-conditioning device |
-
1987
- 1987-01-23 JP JP1247287A patent/JPS63181396A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0195778U (en) * | 1987-12-18 | 1989-06-26 | ||
JPH0521902Y2 (en) * | 1987-12-18 | 1993-06-04 | ||
JP2010283085A (en) * | 2009-06-03 | 2010-12-16 | Toshiba Corp | Electronic apparatus |
JP4676012B2 (en) * | 2009-06-03 | 2011-04-27 | 株式会社東芝 | Electronics |
US8072759B2 (en) | 2009-06-03 | 2011-12-06 | Kabushiki Kaisha Toshiba | Electronic device |
WO2023162029A1 (en) * | 2022-02-22 | 2023-08-31 | 三菱電機株式会社 | Drive device and air-conditioning device |
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