JPS58147141A - Electronic parts - Google Patents

Electronic parts

Info

Publication number
JPS58147141A
JPS58147141A JP57030038A JP3003882A JPS58147141A JP S58147141 A JPS58147141 A JP S58147141A JP 57030038 A JP57030038 A JP 57030038A JP 3003882 A JP3003882 A JP 3003882A JP S58147141 A JPS58147141 A JP S58147141A
Authority
JP
Japan
Prior art keywords
slots
leadframe
resin
lead terminals
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57030038A
Other languages
Japanese (ja)
Inventor
Yasunobu Iwanaga
岩永 康暢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57030038A priority Critical patent/JPS58147141A/en
Publication of JPS58147141A publication Critical patent/JPS58147141A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To produce the electronic parts improving the strength of leading terminal against external force by a method wherein a leadframe is used both as a leading terminal and a part of leadframe is provided with slots to cast exterior resin thereinto. CONSTITUTION:A leadframe 3 coated with insulating resin is provided with several slots extending in parallel with leading terminals in the longitudinal direction while insulating resin is cast into these slots by means of exterior work firmly fixing lead terminals. The slots provided in the lead terminals increase the thermal resistance having little influence upon elements. Besides bonding wire and resin for buffer absorb any thermal distortion while the insulating resin cast into the leadframe slots generates stress against the bending tensile exerted for the lead terminals resisting external force espesially effective for the one exerted in the lateral direction of the lead terminals.

Description

【発明の詳細な説明】 本発明は、電子部品に関し、特にリードフレームによっ
てリード端子を形成し絶縁性樹脂で外装した形態の電子
部品に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic component, and more particularly to an electronic component having lead terminals formed by a lead frame and covered with an insulating resin.

一般に電子部品は、エネルギーの供給を得て増巾、発振
等の能動的機能を発揮する能動電子部品とこれに対称す
る受動電子部品とに大別される。
In general, electronic components are broadly classified into active electronic components that obtain energy supply and perform active functions such as amplification and oscillation, and passive electronic components that are symmetrical to the active electronic components.

前者の能動部品にはトランジスタ、IC等が含まれ、後
者の受動部品には抵抗器、コンデンサ、コイル、ダイオ
ード類等が含まれる。これらの電子部品は所定の機能を
有する素子の電極部分にボンディング法、溶接法、半田
付法の凄続技術を用いてリード端子を接続し、さらに絶
縁性樹脂による外装を施して使用に供する。また使用条
件に応じて素子材料、構造等を選定している。例えば受
動電子部品の一種である磁気抵抗効果素子ではシリコン
基板、ガラス基板あるいはセラミック基板等の平滑な絶
縁性基板上に真空蒸着法あるいはスパッタリング法、を
用いて薄膜抵抗体を形成する。次にこれを抵抗素子とし
てリードフレーム上に傘付け、ボンディングワイヤにて
それぞれの電極部を接続するか、あるいはリード線を外
部リードとして使用する場合は半田付は法にて直接半田
付する。
The former active components include transistors, ICs, etc., and the latter passive components include resistors, capacitors, coils, diodes, etc. These electronic components are put into use by connecting lead terminals to the electrode portions of elements that have a predetermined function using bonding, welding, and soldering techniques, and by covering them with insulating resin. In addition, element materials, structures, etc. are selected depending on usage conditions. For example, in a magnetoresistive element, which is a type of passive electronic component, a thin film resistor is formed on a smooth insulating substrate such as a silicon substrate, a glass substrate, or a ceramic substrate using a vacuum evaporation method or a sputtering method. Next, this is mounted on a lead frame as a resistive element, and the respective electrode parts are connected with bonding wires, or when the lead wires are used as external leads, soldering is performed directly by soldering.

更にしかるべき表面処理を施した後、熱硬化性樹脂で外
装を行い使用に供する。
After further appropriate surface treatment, it is covered with a thermosetting resin and ready for use.

近年の電子部品の小型化に伴ない受動電子部品ある。こ
の為外装方法や外部リード接続方法に工夫がなされ、外
装方法ではディッピング法あるいはトランスファーモー
ルド法に移行している。しかしながら電子部品が小屋化
されるのに伴ない、リード端子の接続!!1mが弱くな
り、実装時には極力、外部から力をかけない様に注意を
払わなければならなくなっている。実装時に力がかかっ
た場合には、リード端子根元と外装樹脂との間にクラッ
クが発生する為、耐湿特性の劣化を招き、故障の原因と
なる等の問題が生じている。
With the miniaturization of electronic components in recent years, there are passive electronic components. For this reason, improvements have been made to the packaging method and external lead connection method, and the packaging method has shifted to the dipping method or transfer molding method. However, as electronic components are becoming more and more compact, it is important to connect lead terminals! ! 1m has become weaker, and care must be taken not to apply external force as much as possible when mounting. If force is applied during mounting, cracks will occur between the base of the lead terminal and the exterior resin, leading to deterioration of moisture resistance and causing problems such as failure.

本発明は、かかる問題を解決する為リード端子をリード
フレームで兼用し、更にリードフレームの一部に長大加
工を行ない、この長大内に外装樹脂を流し込むことによ
り、外力に対しリード端子の強度を向上させた電子部品
を提供する事にある。
In order to solve this problem, the present invention uses a lead frame that also serves as a lead terminal, and also processes a part of the lead frame to make it longer, and pours an exterior resin into the longer part to increase the strength of the lead terminal against external forces. Our goal is to provide improved electronic components.

更に、素子の接続にワイヤーボンディング法も採用する
事が出来る為、温度ストレスに対し順応性の高い電子部
品を提供する事を目的とするものである。
Furthermore, since a wire bonding method can be used to connect elements, the present invention aims to provide electronic components that are highly adaptable to temperature stress.

本発明の要旨は、リード端子となるリードフレーム内に
リード端子長手方向と平−行な位置になるような長大を
設け、外装時に樹脂を長大内に流し込んで構成したもの
である。例えばNi−Fe合金あるいはりン育銅合金等
の金属材料より形成されたリードフレーム上に所定の機
能を有する素子を接着し、素子電極部とリードフレーム
とをワイヤーボンディング工法あるいは半田付工法等の
接続技術を用いて接続する。素子はシリコン基板等の平
滑基板上に絶縁膜を介して形成される。微細パターンを
持つ素子では真空蒸着法あるいはスパッタリング法によ
り薄膜を形成した後フォトリングラフィ技術を利用して
所定のパターンを形成して素子として使用する。又、金
属製マスクを使用し薄膜形成時に同時にパターンを形成
する法や、スクリーン印刷法も使用してもよい6次に素
子表面にバッファーコーティング剤を塗布、乾燥させた
後、トランスファーモールド法あるいはディッピング法
による外装を行う。
The gist of the present invention is to provide an elongated part in a lead frame which becomes a lead terminal so as to be parallel to the longitudinal direction of the lead terminal, and to pour resin into the elongated part at the time of exterior packaging. For example, an element having a predetermined function is bonded onto a lead frame made of a metal material such as a Ni-Fe alloy or a phosphorous copper alloy, and the element electrode part and the lead frame are connected using a wire bonding method, a soldering method, etc. Connect using connection technology. The element is formed on a smooth substrate such as a silicon substrate with an insulating film interposed therebetween. In the case of an element having a fine pattern, a thin film is formed by vacuum evaporation or sputtering, and then a predetermined pattern is formed using photolithography technology and used as an element. Alternatively, a method of forming a pattern at the same time as forming a thin film using a metal mask, or a screen printing method may also be used. 6. After applying a buffer coating agent to the element surface and drying it, transfer molding method or dipping method may be used. Perform exterior packaging according to law.

次に、本発明の実施例を図面を#照して詳細に説明する
Next, embodiments of the present invention will be described in detail with reference to the drawings.

第1図(a)、φ)および第2図(神、(呻はそれぞれ
従来の電子部品の1種である磁気抵抗効果素子の例を示
す断面図及び斜視図である。第1図(a) 、 (b)
の例では、接続工法に半田付工法を採用したもので、平
滑基板2上に薄膜抵抗体lを形成した後、素子電極部4
の部分でリード端子lOと半田付けを行っている。最後
に樹脂材による外装6を施して完成する。又、第2図(
a) 、 (b)の例では、接続工法にボンディング工
法を採用したもので平滑基板2上に薄膜抵抗体1を形成
し、リードフレーム3にダイボンディングを行う。その
後ボンディングワイヤ4により、抵抗素子電極部分とリ
ードフレーム3とを接続する。更に素子保護用樹脂5を
コーティングし、モールド成形を行い、外装6を施して
完了する。このような構成ではリードフレーム3の周囲
に樹脂が単にかぶさっているだけであるためリードフレ
ーム3から伸びたリード端子に外力が加わると、リード
端子の根元で外装樹脂部分が毀損してしまう欠点がある
Figures 1(a) and 2(a) are a cross-sectional view and a perspective view respectively showing an example of a magnetoresistive element, which is a type of conventional electronic component. ), (b)
In this example, the soldering method is used as the connection method, and after forming the thin film resistor l on the smooth substrate 2, the element electrode part 4 is
Soldering is done to the lead terminal IO at the part. Finally, an exterior 6 made of resin material is applied to complete the construction. Also, Figure 2 (
In the examples a) and (b), a bonding method is adopted as the connection method, and a thin film resistor 1 is formed on a smooth substrate 2, and die bonding is performed to a lead frame 3. Thereafter, the resistive element electrode portion and the lead frame 3 are connected using the bonding wire 4 . Further, a resin 5 for protecting the element is coated, molding is performed, and an exterior 6 is applied to complete the process. In such a configuration, since the resin is simply placed around the lead frame 3, if an external force is applied to the lead terminal extending from the lead frame 3, the exterior resin part will be damaged at the base of the lead terminal. be.

′s3図(M) 、 (b)および第4図(a)、Φ)
はそれぞれ本発明の実施例に係る電子部品の断面図およ
び斜視図である。また第3図(C)および第4図(C)
はそれぞれ外装処理前の内部構造を示した斜視図である
's3 Figures (M), (b) and Figure 4 (a), Φ)
1A and 1B are a cross-sectional view and a perspective view, respectively, of an electronic component according to an embodiment of the present invention. Also, Figure 3 (C) and Figure 4 (C)
FIG. 3 is a perspective view showing the internal structure before exterior treatment.

なお、′s3図(a) 〜(C)および!J4図(a)
〜(c)はいずれも双方向リード端子を有する磁気抵抗
効果素子についての実施例を示したものである。シリコ
ン基板等の平滑基板2上に絶縁膜を形成した後、真空蒸
着法あるいはスパッタリング法にて薄膜抵抗体1を形成
する。−次にフォトリソグラフィ技術により微細パター
ンを加工した後パッシベーション膜を付着させ抵抗素子
とする。抵抗素子はダイボンディングによりリードフレ
ーム3に接着し、ボンディングワイヤ4(二より素子電
極部7とリードフレーム3を接続する。更に素子表面に
保護用樹脂5を塗布し乾燥させた後、絶縁性樹脂の外装
6によりモールド成形して使用に供する。第3図(a)
〜(C)および第4図(Jl) 、 (C)に示す如く
、絶縁性樹脂でコートされるリードフレーム3内に、長
軸方向hV゛リード端子と平行にのびた複数個の長穴8
を設けてあり、外装を行う事により、絶縁性樹脂がこの
長大8内に流れ込み、これによってリード端子が強度に
固定される。
In addition, 's3 figures (a) to (C) and! J4 figure (a)
-(c) all show examples of magnetoresistive elements having bidirectional lead terminals. After forming an insulating film on a smooth substrate 2 such as a silicon substrate, a thin film resistor 1 is formed by vacuum evaporation or sputtering. -Next, after processing a fine pattern using photolithography technology, a passivation film is attached to form a resistive element. The resistive element is adhered to the lead frame 3 by die bonding, and the bonding wire 4 (the second wire connects the element electrode part 7 and the lead frame 3).Furthermore, a protective resin 5 is applied to the element surface, and after drying, an insulating resin is applied. It is molded with the outer casing 6 and ready for use. Fig. 3(a)
~(C) and FIGS. 4(Jl) and (C), a plurality of elongated holes 8 are formed in the lead frame 3 coated with an insulating resin, extending in the longitudinal direction hV parallel to the lead terminals.
is provided, and by encasing it, insulating resin flows into this elongated portion 8, thereby firmly fixing the lead terminal.

以上の構造とする事により、熱によるストレス、あるい
は機械的な外力に強いリード端子を有する電子部品が得
られる。温度ストレスに対しては、リード端子内に長穴
を設けた事により、熱抵抗が大きくなり、素子への影響
も少ない、更にボンディングワイヤ、バッファー用樹脂
が熱歪を吸収するとともに、リード端子に加わる曲げ引
張力に対してはリードフレーム長大内の絶縁性樹脂が応
力を発生し外力に対抗する効果を発揮する。%に、リー
ド端子の幅方向から加わる外力に対しては蝦も強固に対
抗することとなる。
With the above structure, it is possible to obtain an electronic component having lead terminals that are resistant to thermal stress or external mechanical force. Regarding temperature stress, the elongated hole in the lead terminal increases thermal resistance and has little effect on the element.Furthermore, the bonding wire and buffer resin absorb thermal strain, and the lead terminal In response to the applied bending tensile force, the insulating resin within the length of the lead frame generates stress and exerts the effect of resisting the external force. %, the shrimp also strongly resists the external force applied from the width direction of the lead terminal.

本発明の電子部品は、リードフレームをリード端子とす
る構造である為、組立工程の自動化が容易であり、大量
生産に適する。又これにより信頼性の高い電子部品を安
値に提供する事が出来る。
Since the electronic component of the present invention has a structure in which the lead frame serves as the lead terminal, the assembly process can be easily automated and is suitable for mass production. This also allows us to provide highly reliable electronic components at low prices.

【図面の簡単な説明】[Brief explanation of drawings]

m1図(&)、Φ)シよび第2図(神、φ)は従来の電
子部品の各種例を示した断面図および斜視図、第3図(
’l) 、 (b) 、 (C)および第4図(a)、
Φ) 、 (C)は本発明の1・・・薄膜抵抗体、2・
・・平滑基板、3・−・リードフレーム、4・・・ボン
ディングワイヤ、6・・・外装、7・・・素子電極部、
8・・・長大。 代理人 弁理士 染 川 利 吉
Fig. m1 (&), Φ) and Fig. 2 (kami, φ) are sectional views and perspective views showing various examples of conventional electronic components, and Fig. 3 (
'l), (b), (C) and Figure 4 (a),
Φ), (C) are 1...thin film resistor of the present invention, 2...
...Smooth substrate, 3...Lead frame, 4...Bonding wire, 6...Exterior, 7...Element electrode part,
8... Long. Agent Patent Attorney Toshiyoshi Somekawa

Claims (1)

【特許請求の範囲】[Claims] リード端子を兼ねたリードフレーム上に部品素子を搭載
し、前記リードフレームと前記部品素子の電IfM部分
とを接続して絶縁性樹脂で外装した電子部品において、
前記リードフレームにリード端子の伸長方向と平行にの
びた長大を形成し、外装時の絶縁性樹脂を前記長大内に
流入せしめたことを%像とする電子部品。
In an electronic component in which a component element is mounted on a lead frame that also serves as a lead terminal, the lead frame and an electric IfM portion of the component element are connected and sheathed with an insulating resin,
An electronic component characterized in that the lead frame is formed with an elongated portion extending parallel to the direction in which the lead terminals extend, and an insulating resin for packaging is allowed to flow into the elongated portion.
JP57030038A 1982-02-26 1982-02-26 Electronic parts Pending JPS58147141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57030038A JPS58147141A (en) 1982-02-26 1982-02-26 Electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57030038A JPS58147141A (en) 1982-02-26 1982-02-26 Electronic parts

Publications (1)

Publication Number Publication Date
JPS58147141A true JPS58147141A (en) 1983-09-01

Family

ID=12292649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57030038A Pending JPS58147141A (en) 1982-02-26 1982-02-26 Electronic parts

Country Status (1)

Country Link
JP (1) JPS58147141A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111738A1 (en) * 1998-08-31 2001-06-27 Rohm Co., Ltd. Semiconductor device and substrate for semiconductor device
WO2004027882A3 (en) * 2002-09-17 2004-07-29 Osram Opto Semiconductors Gmbh Leadframe-based housing, surface-mounted optoelectronic component, and production method
US6984884B2 (en) 2003-06-11 2006-01-10 Mitsubishi Denki Kabushiki Kaisha Electric power semiconductor device
EP1770796A1 (en) * 2005-09-29 2007-04-04 Osram Opto Semiconductors GmbH Radiation-emitting component
JP2009147032A (en) * 2007-12-13 2009-07-02 Panasonic Corp Semiconductor device, and optical pickup device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111738A1 (en) * 1998-08-31 2001-06-27 Rohm Co., Ltd. Semiconductor device and substrate for semiconductor device
EP1111738A4 (en) * 1998-08-31 2006-01-11 Rohm Co Ltd Semiconductor device and substrate for semiconductor device
WO2004027882A3 (en) * 2002-09-17 2004-07-29 Osram Opto Semiconductors Gmbh Leadframe-based housing, surface-mounted optoelectronic component, and production method
US7102213B2 (en) 2002-09-17 2006-09-05 Osram Opto Semiconductors Gmbh Leadframe-based housing, leadframe strip, surface-mounted optoelectronic-component, and production method
CN100449798C (en) * 2002-09-17 2009-01-07 奥斯兰姆奥普托半导体有限责任公司 Leadframe-based component housing, leadframe strip, surface-mounted electronic component, and production method
US6984884B2 (en) 2003-06-11 2006-01-10 Mitsubishi Denki Kabushiki Kaisha Electric power semiconductor device
EP1770796A1 (en) * 2005-09-29 2007-04-04 Osram Opto Semiconductors GmbH Radiation-emitting component
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