JPS63164241U - - Google Patents
Info
- Publication number
- JPS63164241U JPS63164241U JP5705087U JP5705087U JPS63164241U JP S63164241 U JPS63164241 U JP S63164241U JP 5705087 U JP5705087 U JP 5705087U JP 5705087 U JP5705087 U JP 5705087U JP S63164241 U JPS63164241 U JP S63164241U
- Authority
- JP
- Japan
- Prior art keywords
- package
- metal layer
- external lead
- semiconductor element
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 3
- 238000005219 brazing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体素子収納用パツケージ
の絶縁基体の一実施例を示す平面図、第２図は第
１図の絶縁基体を用いた半導体装置の断面図、第
３図は第１図の絶縁基体における外部リード端子
のロウ付け部を示す一部拡大断面図、第４図は従
来の半導体素子収納用パツケージの絶縁基体の平
面図、第５図は第４図の絶縁基体を用いた半導体
装置の断面図、第６図は第４図の絶縁基体におけ
る外部リード端子のロウ付け部を示す一部拡大断
面図である。
１：絶縁基体、２：蓋体、３：絶縁容器、４：
メタライズ金属層、７：外部リード端子、８：ロ
ウ材、Ａ：空間。
FIG. 1 is a plan view showing one embodiment of the insulating base of the package for housing semiconductor elements of the present invention, FIG. 2 is a sectional view of a semiconductor device using the insulating base of FIG. 1, and FIG. 3 is the same as that shown in FIG. FIG. 4 is a plan view of the insulating base of a conventional package for storing semiconductor elements, and FIG. A cross-sectional view of the semiconductor device, FIG. 6 is a partially enlarged cross-sectional view showing the brazed portion of the external lead terminal on the insulating base of FIG. 4. 1: Insulating base, 2: Lid, 3: Insulating container, 4:
Metallized metal layer, 7: external lead terminal, 8: brazing material, A: space.
Claims (1)
部リード端子をロウ付けして成る半導体素子収納
用パツケージにおいて、前記外部リード端子は少
なくともそのロウ付け部が上下両主面の幅寸法を
異にした断面台形形状を成しており、かつ幅寸法
の狭い側の主面がメタライズ金属層側に位置して
いることを特徴とする半導体素子収納用パツケー
ジ。 In a package for housing a semiconductor element, which is formed by brazing a large number of external lead terminals to a metallized metal layer provided in an insulating container, the external lead terminals have a cross section in which at least the brazed portions have different width dimensions on the upper and lower main surfaces. 1. A package for storing a semiconductor element, which has a trapezoidal shape and has a narrower main surface located on a metallized metal layer side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5705087U JPS63164241U (en) | 1987-04-15 | 1987-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5705087U JPS63164241U (en) | 1987-04-15 | 1987-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63164241U true JPS63164241U (en) | 1988-10-26 |
Family
ID=30886401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5705087U Pending JPS63164241U (en) | 1987-04-15 | 1987-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63164241U (en) |
-
1987
- 1987-04-15 JP JP5705087U patent/JPS63164241U/ja active Pending